[llvm] [RISCV][VLOPT] Add support for more SEW=EEW EMUL=EEW instructions in vl-opt-op-info.mir (PR #119416)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 10 09:50:11 PST 2024
https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/119416
>From bca3b7d2e557986b7443ccb271572e7d2eb02c09 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 10 Dec 2024 09:12:31 -0800
Subject: [PATCH 1/3] [RISCV][VLOPT] Add support for vop_vi style instructions
in vl-opt-op-info.mir
---
.../test/CodeGen/RISCV/rvv/vl-opt-op-info.mir | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
index 1071ee53610854..32c5bf2f12e22f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
@@ -1,6 +1,36 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vl-optimizer -verify-machineinstrs | FileCheck %s
+---
+name: vop_vi
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vop_vi
+ ; CHECK: %x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, 1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vr = PseudoVADD_VI_M1 $noreg, %x, 9, 1, 3 /* e8 */, 0 /* tu, mu */
+ %x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, -1, 3 /* e8 */, 0
+ %y:vr = PseudoVADD_VI_M1 $noreg, %x, 9, 1, 3 /* e8 */, 0
+...
+---
+name: vop_vi_incompatible_eew
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vop_vi_incompatible_eew
+ ; CHECK: %x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, -1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vr = PseudoVADD_VI_M1 $noreg, %x, 9, 1, 4 /* e16 */, 0 /* tu, mu */
+ %x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, -1, 3 /* e8 */, 0
+ %y:vr = PseudoVADD_VI_M1 $noreg, %x, 9, 1, 4 /* e16 */, 0
+...
+---
+name: vop_vi_incompatible_emul
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vop_vi_incompatible_emul
+ ; CHECK: %x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, -1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vr = PseudoVADD_VI_MF2 $noreg, %x, 9, 1, 3 /* e8 */, 0 /* tu, mu */
+ %x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, -1, 3 /* e8 */, 0
+ %y:vr = PseudoVADD_VI_MF2 $noreg, %x, 9, 1, 3 /* e8 */, 0
+...
---
name: vop_vv
body: |
>From 17b7d386acbeaeb5b6a11e5a09b276fbe4d25772 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 10 Dec 2024 09:37:26 -0800
Subject: [PATCH 2/3] fixup! test vmerge instructions
---
.../test/CodeGen/RISCV/rvv/vl-opt-op-info.mir | 97 +++++++++++++++++++
1 file changed, 97 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
index 32c5bf2f12e22f..2bf94ab287869e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
@@ -513,3 +513,100 @@ body: |
%x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
%y:vr = PseudoVNSRL_WV_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0
...
+---
+name: vmerge_vim
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vmerge_vim
+ ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VIM_M1 $noreg, %x, 9, $v0, 1, 3 /* e8 */
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
+ %y:vrnov0 = PseudoVMERGE_VIM_M1 $noreg, %x, 9, $v0, 1, 3 /* e8 */
+...
+---
+name: vmerge_vim_incompatible_eew
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vmerge_vim_incompatible_eew
+ ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VIM_M1 $noreg, %x, 9, $v0, 1, 3 /* e8 */
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
+ %y:vrnov0 = PseudoVMERGE_VIM_M1 $noreg, %x, 9, $v0, 1, 3 /* e8 */
+...
+---
+name: vmerge_vim_incompatible_emul
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vmerge_vim_incompatible_emul
+ ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VIM_MF2 $noreg, %x, 9, $v0, 1, 3 /* e8 */
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
+ %y:vrnov0 = PseudoVMERGE_VIM_MF2 $noreg, %x, 9, $v0, 1, 3 /* e8 */
+...
+---
+name: vmerge_vxm
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vmerge_vxm
+ ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:gpr = ADDI $x0, 1
+ ; CHECK-NEXT: %z:vrnov0 = PseudoVMERGE_VXM_M1 $noreg, %x, %y, $v0, 1, 3 /* e8 */
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
+ %y:gpr = ADDI $x0, 1
+ %z:vrnov0 = PseudoVMERGE_VXM_M1 $noreg, %x, %y, $v0, 1, 3 /* e8 */
+...
+---
+name: vmerge_vxm_incompatible_eew
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vmerge_vxm_incompatible_eew
+ ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:gpr = ADDI $x0, 1
+ ; CHECK-NEXT: %z:vrnov0 = PseudoVMERGE_VXM_M1 $noreg, %x, %y, $v0, 1, 3 /* e8 */
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
+ %y:gpr = ADDI $x0, 1
+ %z:vrnov0 = PseudoVMERGE_VXM_M1 $noreg, %x, %y, $v0, 1, 3 /* e8 */
+...
+---
+name: vmerge_vxm_incompatible_emul
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vmerge_vxm_incompatible_emul
+ ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:gpr = ADDI $x0, 1
+ ; CHECK-NEXT: %z:vrnov0 = PseudoVMERGE_VXM_MF2 $noreg, %x, %y, $v0, 1, 3 /* e8 */
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
+ %y:gpr = ADDI $x0, 1
+ %z:vrnov0 = PseudoVMERGE_VXM_MF2 $noreg, %x, %y, $v0, 1, 3 /* e8 */
+...
+---
+name: vmerge_vvm
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vmerge_vvm
+ ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, $noreg, %x, $v0, 1, 3 /* e8 */
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
+ %y:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, $noreg, %x, $v0, 1, 3 /* e8 */
+...
+---
+name: vmerge_vvm_incompatible_eew
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vmerge_vvm_incompatible_eew
+ ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, $noreg, %x, $v0, 1, 3 /* e8 */
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
+ %y:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, $noreg, %x, $v0, 1, 3 /* e8 */
+...
+---
+name: vmerge_vvm_incompatible_emul
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vmerge_vvm_incompatible_emul
+ ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VVM_MF2 $noreg, $noreg, %x, $v0, 1, 3 /* e8 */
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
+ %y:vrnov0 = PseudoVMERGE_VVM_MF2 $noreg, $noreg, %x, $v0, 1, 3 /* e8 */
+...
+
>From c472b5e6a685d8fd927b528102fb5e250fec97a4 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 10 Dec 2024 09:45:00 -0800
Subject: [PATCH 3/3] fixup! test vmv.v.* instructions
---
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 1 +
.../test/CodeGen/RISCV/rvv/vl-opt-op-info.mir | 97 ++++++++++++++++++-
2 files changed, 97 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 62c21fce61c373..7e4d88038804ee 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -331,6 +331,7 @@ static OperandInfo getOperandInfo(const MachineInstr &MI,
case RISCV::VMV_V_I:
case RISCV::VMV_V_V:
case RISCV::VMV_V_X:
+ return OperandInfo(MIVLMul, MILog2SEW);
case RISCV::VSADDU_VI:
case RISCV::VSADDU_VV:
case RISCV::VSADDU_VX:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
index 2bf94ab287869e..7cb36461799dc0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
@@ -609,4 +609,99 @@ body: |
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
%y:vrnov0 = PseudoVMERGE_VVM_MF2 $noreg, $noreg, %x, $v0, 1, 3 /* e8 */
...
-
+---
+name: vmv_v_i
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vmv_v_i
+ ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vr = PseudoVMV_V_I_M1 %x, 9, 1, 3 /* e8 */, 0 /* tu, mu */
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
+ %y:vr = PseudoVMV_V_I_M1 %x, 9, 1, 3 /* e8 */, 0
+...
+---
+name: vmv_v_i_incompatible_eew
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vmv_v_i_incompatible_eew
+ ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vr = PseudoVMV_V_I_M1 %x, 9, 1, 4 /* e16 */, 0 /* tu, mu */
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
+ %y:vr = PseudoVMV_V_I_M1 %x, 9, 1, 4 /* e16 */, 0
+...
+---
+name: vmv_v_i_incompatible_emul
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vmv_v_i_incompatible_emul
+ ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vr = PseudoVMV_V_I_MF2 %x, 9, 1, 3 /* e8 */, 0 /* tu, mu */
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
+ %y:vr = PseudoVMV_V_I_MF2 %x, 9, 1, 3 /* e8 */, 0
+...
+---
+name: vmv_v_x
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vmv_v_x
+ ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:gpr = ADDI $x0, 1
+ ; CHECK-NEXT: %z:vr = PseudoVMV_V_X_M1 %x, %y, 1, 3 /* e8 */, 0 /* tu, mu */
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
+ %y:gpr = ADDI $x0, 1
+ %z:vr = PseudoVMV_V_X_M1 %x, %y, 1, 3 /* e8 */, 0
+...
+---
+name: vmv_v_x_incompatible_eew
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vmv_v_x_incompatible_eew
+ ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:gpr = ADDI $x0, 1
+ ; CHECK-NEXT: %z:vr = PseudoVMV_V_X_M1 %x, %y, 1, 4 /* e16 */, 0 /* tu, mu */
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
+ %y:gpr = ADDI $x0, 1
+ %z:vr = PseudoVMV_V_X_M1 %x, %y, 1, 4 /* e16 */, 0
+...
+---
+name: vmv_v_x_incompatible_emul
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vmv_v_x_incompatible_emul
+ ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:gpr = ADDI $x0, 1
+ ; CHECK-NEXT: %z:vr = PseudoVMV_V_X_MF2 %x, %y, 1, 3 /* e8 */, 0 /* tu, mu */
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
+ %y:gpr = ADDI $x0, 1
+ %z:vr = PseudoVMV_V_X_MF2 %x, %y, 1, 3 /* e8 */, 0
+...
+---
+name: vmv_v_v
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vmv_v_v
+ ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vr = PseudoVMV_V_I_M1 %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
+ %y:vr = PseudoVMV_V_I_M1 %x, $noreg, 1, 3 /* e8 */, 0
+...
+---
+name: vmv_v_v_incompatible_eew
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vmv_v_v_incompatible_eew
+ ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vr = PseudoVMV_V_V_M1 %x, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
+ %y:vr = PseudoVMV_V_V_M1 %x, $noreg, 1, 4 /* e16 */, 0
+...
+---
+name: vmv_v_v_incompatible_emul
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vmv_v_v_incompatible_emul
+ ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vr = PseudoVMV_V_V_MF2 %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
+ %y:vr = PseudoVMV_V_V_MF2 %x, $noreg, 1, 3 /* e8 */, 0
+...
More information about the llvm-commits
mailing list