[llvm] 13539c2 - [RISCV][GISEl] Simplify GISelPredicateCode for binop_with_non_imm12. NFC

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Tue Dec 10 09:44:36 PST 2024


Author: Craig Topper
Date: 2024-12-10T09:44:25-08:00
New Revision: 13539c219c49c581d6ba5270d09b19da9b1e3975

URL: https://github.com/llvm/llvm-project/commit/13539c219c49c581d6ba5270d09b19da9b1e3975
DIFF: https://github.com/llvm/llvm-project/commit/13539c219c49c581d6ba5270d09b19da9b1e3975.diff

LOG: [RISCV][GISEl] Simplify GISelPredicateCode for binop_with_non_imm12. NFC

MRI is already available where this is instantiated.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index c57e7af3c56140..8cefceab43e566 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -188,8 +188,6 @@ class binop_with_non_imm12<SDPatternOperator binop>
   let PredicateCodeUsesOperands = 1;
   let GISelPredicateCode = [{
     const MachineOperand &ImmOp = *Operands[1];
-    const MachineFunction &MF = *MI.getParent()->getParent();
-    const MachineRegisterInfo &MRI = MF.getRegInfo();
 
     if (ImmOp.isReg() && ImmOp.getReg())
       if (auto Val = getIConstantVRegValWithLookThrough(ImmOp.getReg(), MRI)) {


        


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