[llvm] c3175c5 - [InstCombine] Fold `(X & C1) - (X & C2) --> X & (C1 ^ C2)` if `(C1 & C2) == C2` (#119316)

[via llvm-commits]

Author: fengfeng
Date: 2024-12-10T11:06:34+01:00
New Revision: c3175c50a3cefef05046a2f78afb55028b30eb5a

URL: https://github.com/llvm/llvm-project/commit/c3175c50a3cefef05046a2f78afb55028b30eb5a
DIFF: https://github.com/llvm/llvm-project/commit/c3175c50a3cefef05046a2f78afb55028b30eb5a.diff

LOG: [InstCombine] Fold `(X & C1) - (X & C2) --> X & (C1 ^ C2)` if `(C1 & C2) == C2` (#119316)

if (C1 & C2) == C2 then (X & C1) - (X & C2) --> X & (C1 ^ C2)

Alive2: https://alive2.llvm.org/ce/z/JvQU8w

Added: 
    llvm/test/Transforms/InstCombine/and-sub-combine.ll

Modified: 
    llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
index ea7942ef978110..fe0d88fcc6ee4b 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
@@ -2280,6 +2280,16 @@ Instruction *InstCombinerImpl::visitSub(BinaryOperator &I) {
   if (match(Op0, m_OneUse(m_Add(m_Value(X), m_AllOnes()))))
     return BinaryOperator::CreateAdd(Builder.CreateNot(Op1), X);
 
+  // if (C1 & C2) == C2 then (X & C1) - (X & C2) -> X & (C1 ^ C2)
+  Constant *C1, *C2;
+  if (match(Op0, m_And(m_Value(X), m_ImmConstant(C1))) &&
+      match(Op1, m_And(m_Specific(X), m_ImmConstant(C2)))) {
+    Value *AndC = ConstantFoldBinaryInstruction(Instruction::And, C1, C2);
+    if (C2->isElementWiseEqual(AndC))
+      return BinaryOperator::CreateAnd(
+          X, ConstantFoldBinaryInstruction(Instruction::Xor, C1, C2));
+  }
+
   // Reassociate sub/add sequences to create more add instructions and
   // reduce dependency chains:
   // ((X - Y) + Z) - Op1 --> (X + Z) - (Y + Op1)

diff  --git a/llvm/test/Transforms/InstCombine/and-sub-combine.ll b/llvm/test/Transforms/InstCombine/and-sub-combine.ll
new file mode 100644
index 00000000000000..8b2f91b50beef5
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/and-sub-combine.ll
@@ -0,0 +1,83 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+define i8 @and_sub(i8 %a) {
+; CHECK-LABEL: @and_sub(
+; CHECK-NEXT:    [[RET:%.*]] = and i8 [[A:%.*]], 12
+; CHECK-NEXT:    ret i8 [[RET]]
+;
+  %and1 = and i8 %a, 15
+  %and2 = and i8 %a, 3
+
+  %ret = sub i8 %and1, %and2
+  ret i8 %ret
+}
+
+declare void @use(i8)
+define i8 @and_sub_multi_use(i8 %a) {
+; CHECK-LABEL: @and_sub_multi_use(
+; CHECK-NEXT:    [[AND1:%.*]] = and i8 [[A:%.*]], 15
+; CHECK-NEXT:    call void @use(i8 [[AND1]])
+; CHECK-NEXT:    [[AND2:%.*]] = and i8 [[A]], 3
+; CHECK-NEXT:    call void @use(i8 [[AND2]])
+; CHECK-NEXT:    [[RET:%.*]] = and i8 [[A]], 12
+; CHECK-NEXT:    ret i8 [[RET]]
+;
+  %and1 = and i8 %a, 15
+  call void @use(i8 %and1)
+  %and2 = and i8 %a, 3
+  call void @use(i8 %and2)
+  %ret = sub i8 %and1, %and2
+  ret i8 %ret
+}
+
+define <2 x i32> @and_sub_vec(<2 x i32> %a) {
+; CHECK-LABEL: @and_sub_vec(
+; CHECK-NEXT:    [[RET:%.*]] = and <2 x i32> [[A:%.*]], <i32 3, i32 8>
+; CHECK-NEXT:    ret <2 x i32> [[RET]]
+;
+  %and1 = and <2 x i32> %a, <i32 11, i32 10>
+  %and2 = and <2 x i32> %a, <i32 8, i32 2>
+
+  %ret = sub <2 x i32> %and1, %and2
+  ret <2 x i32> %ret
+}
+
+define <2 x i32> @and_sub_vec_posion(<2 x i32> %a) {
+; CHECK-LABEL: @and_sub_vec_posion(
+; CHECK-NEXT:    ret <2 x i32> poison
+;
+  %and1 = and <2 x i32> %a, <i32 11, i32 poison>
+  %and2 = and <2 x i32> %a, <i32 poison, i32 2>
+
+  %ret = sub <2 x i32> %and1, %and2
+  ret <2 x i32> %ret
+}
+
+define <2 x i32> @and_sub_vec_undef(<2 x i32> %a) {
+; CHECK-LABEL: @and_sub_vec_undef(
+; CHECK-NEXT:    [[AND1:%.*]] = and <2 x i32> [[A:%.*]], <i32 11, i32 undef>
+; CHECK-NEXT:    [[AND2:%.*]] = and <2 x i32> [[A]], <i32 undef, i32 2>
+; CHECK-NEXT:    [[RET:%.*]] = sub <2 x i32> [[AND1]], [[AND2]]
+; CHECK-NEXT:    ret <2 x i32> [[RET]]
+;
+  %and1 = and <2 x i32> %a, <i32 11, i32 undef>
+  %and2 = and <2 x i32> %a, <i32 undef, i32 2>
+
+  %ret = sub <2 x i32> %and1, %and2
+  ret <2 x i32> %ret
+}
+
+define i8 @and_sub_negtive(i8 %a) {
+; CHECK-LABEL: @and_sub_negtive(
+; CHECK-NEXT:    [[AND1:%.*]] = and i8 [[A:%.*]], 10
+; CHECK-NEXT:    [[AND2:%.*]] = and i8 [[A]], 9
+; CHECK-NEXT:    [[RET:%.*]] = sub nsw i8 [[AND1]], [[AND2]]
+; CHECK-NEXT:    ret i8 [[RET]]
+;
+  %and1 = and i8 %a, 10
+  %and2 = and i8 %a, 9
+
+  %ret = sub i8 %and1, %and2
+  ret i8 %ret
+}