[llvm] Reapply "Reapply "[AMDGPU] prevent shrinking udiv/urem if either oper… (PR #119325)

[Jay Foad via llvm-commits]

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@@ -1220,7 +1236,7 @@ Value *AMDGPUCodeGenPrepareImpl::expandDivRem24(IRBuilder<> &Builder,
   // If Num bits <= 24, assume 0 signbits.
   unsigned AtLeast = (SSBits <= 24) ? 0 : (SSBits - 24 + IsSigned);
   int DivBits = getDivNumBits(I, Num, Den, AtLeast, IsSigned);
-  if (DivBits == -1)
+  if (DivBits == -1 || DivBits > 24)
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jayfoad wrote:

PLEASE take a moment to simplify things by cleaning up the API of `getDivNumBits`, instead of just adding extra checks.

`getDivNumBits` should return unsigned. There is no need for the special -1 return value, since returning bitwidth is always a safe default value. Then all callers can just check exactly what they need, e.g. DivBits <= 24 if they want to optimize to a 24-bit divide.

The `AtLeast` argument should be a hint for the max _return_ value that is interesting, e.g. for a caller trying to optimize 32 bit divide to 24 bit divide they should pass in 24 (not 8). That will remove confusion about whether the value passed in should depend on IsSigned or not -- currently different callers do different things.

This can be done as an NFC cleanup before resubmitting your patch.

https://github.com/llvm/llvm-project/pull/119325