[llvm] [GISel] Support narrowing G_ICMP with more than 2 parts. (PR #119335)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 9 23:11:41 PST 2024
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/119335
>From fa8e465a27f00e5d6209f604357db093dc8a3baa Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 9 Dec 2024 21:04:59 -0800
Subject: [PATCH 1/2] [GISel] Support narrowing G_ICMP with more than 2 parts.
This allows us to support i128 G_ICMP on RV32. I'm not sure how to
test the "left over" part of this as RISC-V always widens to a power of 2
before narrowing.
---
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 72 ++++--
.../AArch64/Atomics/aarch64-atomicrmw-lse2.ll | 80 +++----
.../Atomics/aarch64-atomicrmw-lse2_lse128.ll | 80 +++----
.../aarch64-atomicrmw-outline_atomics.ll | 80 +++----
.../AArch64/Atomics/aarch64-atomicrmw-rcpc.ll | 80 +++----
.../Atomics/aarch64-atomicrmw-rcpc3.ll | 80 +++----
.../Atomics/aarch64-atomicrmw-v8_1a.ll | 80 +++----
.../AArch64/Atomics/aarch64-atomicrmw-v8a.ll | 80 +++----
.../AArch64/GlobalISel/legalize-cmp.mir | 8 +-
.../GlobalISel/legalize-threeway-cmp.mir | 16 +-
llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll | 28 +--
llvm/test/CodeGen/AArch64/icmp.ll | 32 ++-
llvm/test/CodeGen/AArch64/scmp.ll | 14 +-
llvm/test/CodeGen/AArch64/ucmp.ll | 28 +--
.../AArch64/vecreduce-umax-legalization.ll | 7 +-
.../test/CodeGen/AMDGPU/GlobalISel/saddsat.ll | 192 ++++++++--------
.../test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll | 210 +++++++++---------
llvm/test/CodeGen/AMDGPU/div_i128.ll | 90 ++++----
.../Mips/GlobalISel/legalizer/icmp.mir | 64 +++---
.../CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll | 24 +-
.../legalizer/legalize-addo-subo-rv32.mir | 48 ++--
.../legalizer/legalize-icmp-rv32.mir | 178 +++++++++------
.../legalizer/legalize-icmp-rv64.mir | 192 ++++++++--------
.../legalizer/legalize-sat-rv32.mir | 48 ++--
.../legalizer/legalize-smax-rv32.mir | 8 +-
.../legalizer/legalize-smin-rv32.mir | 8 +-
.../legalizer/legalize-umax-rv32.mir | 8 +-
.../legalizer/legalize-umin-rv32.mir | 8 +-
llvm/test/CodeGen/X86/isel-select-cmov.ll | 24 +-
29 files changed, 970 insertions(+), 897 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 5bfeee05a19c0d..a6997b7a27d450 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -1717,14 +1717,9 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
case TargetOpcode::G_ICMP: {
Register LHS = MI.getOperand(2).getReg();
LLT SrcTy = MRI.getType(LHS);
- uint64_t SrcSize = SrcTy.getSizeInBits();
CmpInst::Predicate Pred =
static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
- // TODO: Handle the non-equality case for weird sizes.
- if (NarrowSize * 2 != SrcSize && !ICmpInst::isEquality(Pred))
- return UnableToLegalize;
-
LLT LeftoverTy; // Example: s88 -> s64 (NarrowTy) + s24 (leftover)
SmallVector<Register, 4> LHSPartRegs, LHSLeftoverRegs;
if (!extractParts(LHS, SrcTy, NarrowTy, LeftoverTy, LHSPartRegs,
@@ -1776,19 +1771,60 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
Or = MIRBuilder.buildOr(NarrowTy, Or, Xors[I]);
MIRBuilder.buildICmp(Pred, Dst, Or, Zero);
} else {
- // TODO: Handle non-power-of-two types.
- assert(LHSPartRegs.size() == 2 && "Expected exactly 2 LHS part regs?");
- assert(RHSPartRegs.size() == 2 && "Expected exactly 2 RHS part regs?");
- Register LHSL = LHSPartRegs[0];
- Register LHSH = LHSPartRegs[1];
- Register RHSL = RHSPartRegs[0];
- Register RHSH = RHSPartRegs[1];
- MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, ResTy, LHSH, RHSH);
- MachineInstrBuilder CmpHEQ =
- MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy, LHSH, RHSH);
- MachineInstrBuilder CmpLU = MIRBuilder.buildICmp(
- ICmpInst::getUnsignedPredicate(Pred), ResTy, LHSL, RHSL);
- MIRBuilder.buildSelect(Dst, CmpHEQ, CmpLU, CmpH);
+ Register CmpIn;
+ for (unsigned I = 0, E = LHSPartRegs.size(); I != E; ++I) {
+ Register CmpOut;
+ CmpInst::Predicate PartPred;
+
+ if (I == E - 1 && LHSLeftoverRegs.empty()) {
+ PartPred = Pred;
+ CmpOut = Dst;
+ } else {
+ PartPred = ICmpInst::getUnsignedPredicate(Pred);
+ CmpOut = MRI.createGenericVirtualRegister(ResTy);
+ }
+
+ if (!CmpIn) {
+ MIRBuilder.buildICmp(PartPred, CmpOut,
+ LHSPartRegs[I], RHSPartRegs[I]);
+ } else {
+ auto Cmp =
+ MIRBuilder.buildICmp(PartPred, ResTy,
+ LHSPartRegs[I], RHSPartRegs[I]);
+ auto CmpEq = MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy,
+ LHSPartRegs[I], RHSPartRegs[I]);
+ MIRBuilder.buildSelect(CmpOut, CmpEq, CmpIn, Cmp);
+ }
+
+ CmpIn = CmpOut;
+ }
+
+ for (unsigned I = 0, E = LHSLeftoverRegs.size(); I != E; ++I) {
+ Register CmpOut;
+ CmpInst::Predicate PartPred;
+
+ if (I == E - 1 && LHSLeftoverRegs.empty()) {
+ PartPred = Pred;
+ CmpOut = Dst;
+ } else {
+ PartPred = ICmpInst::getUnsignedPredicate(Pred);
+ CmpOut = MRI.createGenericVirtualRegister(ResTy);
+ }
+
+ if (!CmpIn) {
+ MIRBuilder.buildICmp(PartPred, CmpOut,
+ LHSLeftoverRegs[I], RHSLeftoverRegs[I]);
+ } else {
+ auto Cmp =
+ MIRBuilder.buildICmp(PartPred, ResTy,
+ LHSLeftoverRegs[I], RHSLeftoverRegs[I]);
+ auto CmpEq = MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy,
+ LHSLeftoverRegs[I], RHSLeftoverRegs[I]);
+ MIRBuilder.buildSelect(CmpOut, CmpEq, CmpIn, Cmp);
+ }
+
+ CmpIn = CmpOut;
+ }
}
MI.eraseFromParent();
return Legalized;
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
index 88061756d8feeb..d93ef6f8b2869b 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
@@ -5755,8 +5755,8 @@ define dso_local i64 @atomicrmw_max_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_monotonic:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -5785,8 +5785,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acquire:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -5815,8 +5815,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_release:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -5845,8 +5845,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acq_rel:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -5875,8 +5875,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_seq_cst:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -6230,8 +6230,8 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6252,8 +6252,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6274,8 +6274,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6296,8 +6296,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6318,8 +6318,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6725,8 +6725,8 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_monotonic:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -6755,8 +6755,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acquire:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -6785,8 +6785,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_release:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -6815,8 +6815,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acq_rel:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -6845,8 +6845,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_seq_cst:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -7200,8 +7200,8 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -7222,8 +7222,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -7244,8 +7244,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -7266,8 +7266,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -7288,8 +7288,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -7690,8 +7690,8 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_monotonic:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -7720,8 +7720,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acquire:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -7750,8 +7750,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_release:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -7780,8 +7780,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acq_rel:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -7810,8 +7810,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_seq_cst:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -8160,8 +8160,8 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -8182,8 +8182,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -8204,8 +8204,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -8226,8 +8226,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -8248,8 +8248,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -8650,8 +8650,8 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_monotonic:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -8680,8 +8680,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acquire:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -8710,8 +8710,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_release:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -8740,8 +8740,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -8770,8 +8770,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -9120,8 +9120,8 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -9142,8 +9142,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -9164,8 +9164,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -9186,8 +9186,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -9208,8 +9208,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
index a1712a5ec7a27c..1fad4a6b54f6b4 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
@@ -3930,8 +3930,8 @@ define dso_local i64 @atomicrmw_max_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_monotonic:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -3958,8 +3958,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acquire:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -3986,8 +3986,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_release:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -4014,8 +4014,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acq_rel:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -4042,8 +4042,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_seq_cst:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -4325,8 +4325,8 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -4347,8 +4347,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -4369,8 +4369,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -4391,8 +4391,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -4413,8 +4413,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -4575,8 +4575,8 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_monotonic:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -4603,8 +4603,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acquire:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -4631,8 +4631,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_release:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -4659,8 +4659,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acq_rel:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -4687,8 +4687,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_seq_cst:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -4970,8 +4970,8 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -4992,8 +4992,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -5014,8 +5014,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -5036,8 +5036,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -5058,8 +5058,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -5220,8 +5220,8 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_monotonic:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -5248,8 +5248,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acquire:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -5276,8 +5276,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_release:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -5304,8 +5304,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acq_rel:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -5332,8 +5332,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_seq_cst:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -5610,8 +5610,8 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -5632,8 +5632,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -5654,8 +5654,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -5676,8 +5676,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -5698,8 +5698,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -5860,8 +5860,8 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_monotonic:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -5888,8 +5888,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acquire:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -5916,8 +5916,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_release:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -5944,8 +5944,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -5972,8 +5972,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -6250,8 +6250,8 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6272,8 +6272,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6294,8 +6294,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6316,8 +6316,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6338,8 +6338,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll
index e9b096e8c6c44b..4605bdd2f6073f 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll
@@ -4390,8 +4390,8 @@ define dso_local i64 @atomicrmw_max_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_monotonic:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x11
+; -O0: subs x10, x10, x9
; -O0: subs x12, x12, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w12, w10, #0x1
@@ -4416,8 +4416,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acquire:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x11
+; -O0: subs x10, x10, x9
; -O0: subs x12, x12, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w12, w10, #0x1
@@ -4442,8 +4442,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_release:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x11
+; -O0: subs x10, x10, x9
; -O0: subs x12, x12, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w12, w10, #0x1
@@ -4468,8 +4468,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acq_rel:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x11
+; -O0: subs x10, x10, x9
; -O0: subs x12, x12, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w12, w10, #0x1
@@ -4494,8 +4494,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_seq_cst:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x11
+; -O0: subs x10, x10, x9
; -O0: subs x12, x12, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w12, w10, #0x1
@@ -4835,8 +4835,8 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -4857,8 +4857,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -4879,8 +4879,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -4901,8 +4901,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -4923,8 +4923,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -5290,8 +5290,8 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_monotonic:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x11
+; -O0: subs x10, x10, x9
; -O0: subs x12, x12, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w12, w10, #0x1
@@ -5316,8 +5316,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acquire:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x11
+; -O0: subs x10, x10, x9
; -O0: subs x12, x12, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w12, w10, #0x1
@@ -5342,8 +5342,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_release:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x11
+; -O0: subs x10, x10, x9
; -O0: subs x12, x12, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w12, w10, #0x1
@@ -5368,8 +5368,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acq_rel:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x11
+; -O0: subs x10, x10, x9
; -O0: subs x12, x12, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w12, w10, #0x1
@@ -5394,8 +5394,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_seq_cst:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x11
+; -O0: subs x10, x10, x9
; -O0: subs x12, x12, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w12, w10, #0x1
@@ -5735,8 +5735,8 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -5757,8 +5757,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -5779,8 +5779,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -5801,8 +5801,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -5823,8 +5823,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6185,8 +6185,8 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_monotonic:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x11
+; -O0: subs x10, x10, x9
; -O0: subs x12, x12, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w12, w10, #0x1
@@ -6211,8 +6211,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acquire:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x11
+; -O0: subs x10, x10, x9
; -O0: subs x12, x12, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w12, w10, #0x1
@@ -6237,8 +6237,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_release:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x11
+; -O0: subs x10, x10, x9
; -O0: subs x12, x12, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w12, w10, #0x1
@@ -6263,8 +6263,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acq_rel:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x11
+; -O0: subs x10, x10, x9
; -O0: subs x12, x12, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w12, w10, #0x1
@@ -6289,8 +6289,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_seq_cst:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x11
+; -O0: subs x10, x10, x9
; -O0: subs x12, x12, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w12, w10, #0x1
@@ -6625,8 +6625,8 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6647,8 +6647,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6669,8 +6669,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6691,8 +6691,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6713,8 +6713,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -7075,8 +7075,8 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_monotonic:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x11
+; -O0: subs x10, x10, x9
; -O0: subs x12, x12, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w12, w10, #0x1
@@ -7101,8 +7101,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acquire:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x11
+; -O0: subs x10, x10, x9
; -O0: subs x12, x12, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w12, w10, #0x1
@@ -7127,8 +7127,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_release:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x11
+; -O0: subs x10, x10, x9
; -O0: subs x12, x12, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w12, w10, #0x1
@@ -7153,8 +7153,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x11
+; -O0: subs x10, x10, x9
; -O0: subs x12, x12, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w12, w10, #0x1
@@ -7179,8 +7179,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x11
+; -O0: subs x10, x10, x9
; -O0: subs x12, x12, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w12, w10, #0x1
@@ -7515,8 +7515,8 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -7537,8 +7537,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -7559,8 +7559,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -7581,8 +7581,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -7603,8 +7603,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
index 4f9e520997a22f..912d87dcd2b9b6 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
@@ -5755,8 +5755,8 @@ define dso_local i64 @atomicrmw_max_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_monotonic:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -5785,8 +5785,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acquire:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -5815,8 +5815,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_release:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -5845,8 +5845,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acq_rel:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -5875,8 +5875,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_seq_cst:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -6230,8 +6230,8 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6252,8 +6252,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6274,8 +6274,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6296,8 +6296,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6318,8 +6318,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6725,8 +6725,8 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_monotonic:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -6755,8 +6755,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acquire:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -6785,8 +6785,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_release:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -6815,8 +6815,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acq_rel:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -6845,8 +6845,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_seq_cst:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -7200,8 +7200,8 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -7222,8 +7222,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -7244,8 +7244,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -7266,8 +7266,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -7288,8 +7288,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -7690,8 +7690,8 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_monotonic:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -7720,8 +7720,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acquire:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -7750,8 +7750,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_release:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -7780,8 +7780,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acq_rel:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -7810,8 +7810,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_seq_cst:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -8160,8 +8160,8 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -8182,8 +8182,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -8204,8 +8204,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -8226,8 +8226,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -8248,8 +8248,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -8650,8 +8650,8 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_monotonic:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -8680,8 +8680,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acquire:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -8710,8 +8710,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_release:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -8740,8 +8740,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -8770,8 +8770,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -9120,8 +9120,8 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -9142,8 +9142,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -9164,8 +9164,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -9186,8 +9186,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -9208,8 +9208,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
index 3437ccc8be40d7..725558f2dcf727 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
@@ -5755,8 +5755,8 @@ define dso_local i64 @atomicrmw_max_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_monotonic:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -5785,8 +5785,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acquire:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -5815,8 +5815,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_release:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -5845,8 +5845,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acq_rel:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -5875,8 +5875,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_seq_cst:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -6230,8 +6230,8 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6252,8 +6252,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6274,8 +6274,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6296,8 +6296,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6318,8 +6318,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6725,8 +6725,8 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_monotonic:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -6755,8 +6755,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acquire:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -6785,8 +6785,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_release:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -6815,8 +6815,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acq_rel:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -6845,8 +6845,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_seq_cst:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -7200,8 +7200,8 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -7222,8 +7222,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -7244,8 +7244,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -7266,8 +7266,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -7288,8 +7288,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -7690,8 +7690,8 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_monotonic:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -7720,8 +7720,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acquire:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -7750,8 +7750,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_release:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -7780,8 +7780,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acq_rel:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -7810,8 +7810,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_seq_cst:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -8160,8 +8160,8 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -8182,8 +8182,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -8204,8 +8204,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -8226,8 +8226,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -8248,8 +8248,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -8650,8 +8650,8 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_monotonic:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -8680,8 +8680,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acquire:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -8710,8 +8710,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_release:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -8740,8 +8740,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -8770,8 +8770,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -9120,8 +9120,8 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -9142,8 +9142,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -9164,8 +9164,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -9186,8 +9186,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -9208,8 +9208,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
index ee5fbe39b4492c..51933261313ea3 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
@@ -4055,8 +4055,8 @@ define dso_local i64 @atomicrmw_max_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_monotonic:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -4083,8 +4083,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acquire:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -4111,8 +4111,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_release:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -4139,8 +4139,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acq_rel:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -4167,8 +4167,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_seq_cst:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -4450,8 +4450,8 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -4472,8 +4472,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -4494,8 +4494,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -4516,8 +4516,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -4538,8 +4538,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -4700,8 +4700,8 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_monotonic:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -4728,8 +4728,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acquire:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -4756,8 +4756,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_release:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -4784,8 +4784,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acq_rel:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -4812,8 +4812,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_seq_cst:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -5095,8 +5095,8 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -5117,8 +5117,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -5139,8 +5139,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -5161,8 +5161,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -5183,8 +5183,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -5345,8 +5345,8 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_monotonic:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -5373,8 +5373,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acquire:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -5401,8 +5401,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_release:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -5429,8 +5429,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acq_rel:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -5457,8 +5457,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_seq_cst:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -5735,8 +5735,8 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -5757,8 +5757,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -5779,8 +5779,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -5801,8 +5801,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -5823,8 +5823,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -5985,8 +5985,8 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_monotonic:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -6013,8 +6013,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acquire:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -6041,8 +6041,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_release:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -6069,8 +6069,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -6097,8 +6097,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
-; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
+; -O0: subs x11, x11, x10
; -O0: subs x13, x13, x10
; -O0: csel w11, w9, w11, eq
; -O0: ands w13, w11, #0x1
@@ -6375,8 +6375,8 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6397,8 +6397,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6419,8 +6419,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6441,8 +6441,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6463,8 +6463,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
index 2473147509dc87..004e433d9408a6 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
@@ -5755,8 +5755,8 @@ define dso_local i64 @atomicrmw_max_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_monotonic:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -5785,8 +5785,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acquire:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -5815,8 +5815,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_release:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -5845,8 +5845,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acq_rel:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -5875,8 +5875,8 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_seq_cst:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -6230,8 +6230,8 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6252,8 +6252,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6274,8 +6274,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6296,8 +6296,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6318,8 +6318,8 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -6725,8 +6725,8 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_monotonic:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -6755,8 +6755,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acquire:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -6785,8 +6785,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_release:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -6815,8 +6815,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acq_rel:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -6845,8 +6845,8 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_seq_cst:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -7200,8 +7200,8 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -7222,8 +7222,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -7244,8 +7244,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -7266,8 +7266,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -7288,8 +7288,8 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -7690,8 +7690,8 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_monotonic:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -7720,8 +7720,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acquire:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -7750,8 +7750,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_release:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -7780,8 +7780,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acq_rel:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -7810,8 +7810,8 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_seq_cst:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -8160,8 +8160,8 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -8182,8 +8182,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -8204,8 +8204,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -8226,8 +8226,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -8248,8 +8248,8 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -8650,8 +8650,8 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_monotonic:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -8680,8 +8680,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acquire:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -8710,8 +8710,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_release:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -8740,8 +8740,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -8770,8 +8770,8 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
-; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
+; -O0: subs x10, x10, x9
; -O0: subs x13, x13, x9
; -O0: csel w10, w8, w10, eq
; -O0: ands w13, w10, #0x1
@@ -9120,8 +9120,8 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -9142,8 +9142,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acquire:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -9164,8 +9164,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_release:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -9186,8 +9186,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
@@ -9208,8 +9208,8 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
-; -O0: subs x8, x8, x10
; -O0: subs x8, x8, x9
+; -O0: subs x11, x11, x10
; -O0: subs x12, x12, x10
; -O0: csel w11, w8, w11, eq
; -O0: ands w12, w11, #0x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
index bd80a892e239e4..d96f6fbc12c7ca 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
@@ -47,10 +47,10 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967296
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[DEF]](s64), [[C1]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[DEF]](s64), [[C1]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[DEF]](s64), [[C]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[DEF]](s64), [[C]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[DEF]](s64), [[C1]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[DEF]](s64), [[C1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; CHECK-NEXT: G_BRCOND [[SELECT]](s32), %bb.1
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-threeway-cmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-threeway-cmp.mir
index e69f79bdd187a3..18c4f3c31efa53 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-threeway-cmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-threeway-cmp.mir
@@ -121,17 +121,17 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[DEF]](s64), [[DEF]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[DEF]](s64), [[DEF]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s64), [[COPY1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s64), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[DEF]](s64), [[DEF]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[DEF]](s64), [[DEF]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[C]], [[C1]]
- ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[DEF]](s64), [[DEF]]
- ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[DEF]](s64), [[DEF]]
- ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]]
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s32), [[ICMP5]], [[ICMP3]]
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[DEF]](s64), [[DEF]]
+ ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[DEF]](s64), [[DEF]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s32), [[ICMP3]], [[ICMP4]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[SELECT2]](s32), [[C2]], [[SELECT1]]
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SELECT3]], 2
diff --git a/llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll b/llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
index f7aa57a068a4ce..8a503bb65c079e 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
@@ -784,12 +784,11 @@ define i128 @sminv_v2i128(<2 x i128> %a) {
;
; CHECK-GI-LABEL: sminv_v2i128:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: cmp x1, x3
-; CHECK-GI-NEXT: cset w8, lt
; CHECK-GI-NEXT: cmp x0, x2
-; CHECK-GI-NEXT: cset w9, lo
+; CHECK-GI-NEXT: cset w8, lo
; CHECK-GI-NEXT: cmp x1, x3
-; CHECK-GI-NEXT: csel w8, w9, w8, eq
+; CHECK-GI-NEXT: cset w9, lt
+; CHECK-GI-NEXT: csel w8, w8, w9, eq
; CHECK-GI-NEXT: tst w8, #0x1
; CHECK-GI-NEXT: csel x0, x0, x2, ne
; CHECK-GI-NEXT: csel x1, x1, x3, ne
@@ -1145,12 +1144,11 @@ define i128 @smaxv_v2i128(<2 x i128> %a) {
;
; CHECK-GI-LABEL: smaxv_v2i128:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: cmp x1, x3
-; CHECK-GI-NEXT: cset w8, gt
; CHECK-GI-NEXT: cmp x0, x2
-; CHECK-GI-NEXT: cset w9, hi
+; CHECK-GI-NEXT: cset w8, hi
; CHECK-GI-NEXT: cmp x1, x3
-; CHECK-GI-NEXT: csel w8, w9, w8, eq
+; CHECK-GI-NEXT: cset w9, gt
+; CHECK-GI-NEXT: csel w8, w8, w9, eq
; CHECK-GI-NEXT: tst w8, #0x1
; CHECK-GI-NEXT: csel x0, x0, x2, ne
; CHECK-GI-NEXT: csel x1, x1, x3, ne
@@ -1504,12 +1502,11 @@ define i128 @uminv_v2i128(<2 x i128> %a) {
;
; CHECK-GI-LABEL: uminv_v2i128:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: cmp x1, x3
-; CHECK-GI-NEXT: cset w8, lo
; CHECK-GI-NEXT: cmp x0, x2
-; CHECK-GI-NEXT: cset w9, lo
+; CHECK-GI-NEXT: cset w8, lo
; CHECK-GI-NEXT: cmp x1, x3
-; CHECK-GI-NEXT: csel w8, w9, w8, eq
+; CHECK-GI-NEXT: cset w9, lo
+; CHECK-GI-NEXT: csel w8, w8, w9, eq
; CHECK-GI-NEXT: tst w8, #0x1
; CHECK-GI-NEXT: csel x0, x0, x2, ne
; CHECK-GI-NEXT: csel x1, x1, x3, ne
@@ -1861,12 +1858,11 @@ define i128 @umaxv_v2i128(<2 x i128> %a) {
;
; CHECK-GI-LABEL: umaxv_v2i128:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: cmp x1, x3
-; CHECK-GI-NEXT: cset w8, hi
; CHECK-GI-NEXT: cmp x0, x2
-; CHECK-GI-NEXT: cset w9, hi
+; CHECK-GI-NEXT: cset w8, hi
; CHECK-GI-NEXT: cmp x1, x3
-; CHECK-GI-NEXT: csel w8, w9, w8, eq
+; CHECK-GI-NEXT: cset w9, hi
+; CHECK-GI-NEXT: csel w8, w8, w9, eq
; CHECK-GI-NEXT: tst w8, #0x1
; CHECK-GI-NEXT: csel x0, x0, x2, ne
; CHECK-GI-NEXT: csel x1, x1, x3, ne
diff --git a/llvm/test/CodeGen/AArch64/icmp.ll b/llvm/test/CodeGen/AArch64/icmp.ll
index 61964060ca2c8b..e284795760c5ca 100644
--- a/llvm/test/CodeGen/AArch64/icmp.ll
+++ b/llvm/test/CodeGen/AArch64/icmp.ll
@@ -1403,28 +1403,26 @@ define <2 x i128> @v2i128_i128(<2 x i128> %a, <2 x i128> %b, <2 x i128> %d, <2 x
;
; CHECK-GI-LABEL: v2i128_i128:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: cmp x1, x5
-; CHECK-GI-NEXT: ldp x8, x9, [sp]
-; CHECK-GI-NEXT: cset w10, lt
; CHECK-GI-NEXT: cmp x0, x4
-; CHECK-GI-NEXT: cset w13, lo
+; CHECK-GI-NEXT: ldp x9, x10, [sp]
+; CHECK-GI-NEXT: cset w8, lo
; CHECK-GI-NEXT: cmp x1, x5
-; CHECK-GI-NEXT: csel w10, w13, w10, eq
-; CHECK-GI-NEXT: cmp x3, x7
-; CHECK-GI-NEXT: ldp x13, x14, [sp, #32]
-; CHECK-GI-NEXT: cset w15, lt
+; CHECK-GI-NEXT: cset w11, lt
+; CHECK-GI-NEXT: ldp x14, x15, [sp, #32]
+; CHECK-GI-NEXT: csel w8, w8, w11, eq
; CHECK-GI-NEXT: cmp x2, x6
-; CHECK-GI-NEXT: ldp x11, x12, [sp, #16]
-; CHECK-GI-NEXT: cset w16, lo
+; CHECK-GI-NEXT: cset w11, lo
; CHECK-GI-NEXT: cmp x3, x7
+; CHECK-GI-NEXT: ldp x12, x13, [sp, #16]
+; CHECK-GI-NEXT: cset w16, lt
; CHECK-GI-NEXT: ldp x17, x18, [sp, #48]
-; CHECK-GI-NEXT: csel w15, w16, w15, eq
-; CHECK-GI-NEXT: tst w10, #0x1
-; CHECK-GI-NEXT: csel x0, x8, x13, ne
-; CHECK-GI-NEXT: csel x1, x9, x14, ne
-; CHECK-GI-NEXT: tst w15, #0x1
-; CHECK-GI-NEXT: csel x2, x11, x17, ne
-; CHECK-GI-NEXT: csel x3, x12, x18, ne
+; CHECK-GI-NEXT: csel w11, w11, w16, eq
+; CHECK-GI-NEXT: tst w8, #0x1
+; CHECK-GI-NEXT: csel x0, x9, x14, ne
+; CHECK-GI-NEXT: csel x1, x10, x15, ne
+; CHECK-GI-NEXT: tst w11, #0x1
+; CHECK-GI-NEXT: csel x2, x12, x17, ne
+; CHECK-GI-NEXT: csel x3, x13, x18, ne
; CHECK-GI-NEXT: ret
entry:
%c = icmp slt <2 x i128> %a, %b
diff --git a/llvm/test/CodeGen/AArch64/scmp.ll b/llvm/test/CodeGen/AArch64/scmp.ll
index 4aff5a836e1a18..be167fde7dbe6d 100644
--- a/llvm/test/CodeGen/AArch64/scmp.ll
+++ b/llvm/test/CodeGen/AArch64/scmp.ll
@@ -79,20 +79,18 @@ define i8 @scmp.8.128(i128 %x, i128 %y) nounwind {
;
; CHECK-GI-LABEL: scmp.8.128:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: cmp x1, x3
-; CHECK-GI-NEXT: cset w8, gt
; CHECK-GI-NEXT: cmp x0, x2
-; CHECK-GI-NEXT: cset w9, hi
+; CHECK-GI-NEXT: cset w8, hi
; CHECK-GI-NEXT: cmp x1, x3
-; CHECK-GI-NEXT: csel w8, w9, w8, eq
+; CHECK-GI-NEXT: cset w9, gt
+; CHECK-GI-NEXT: csel w8, w8, w9, eq
; CHECK-GI-NEXT: tst w8, #0x1
; CHECK-GI-NEXT: cset w8, ne
-; CHECK-GI-NEXT: cmp x1, x3
-; CHECK-GI-NEXT: cset w9, lt
; CHECK-GI-NEXT: cmp x0, x2
-; CHECK-GI-NEXT: cset w10, lo
+; CHECK-GI-NEXT: cset w9, lo
; CHECK-GI-NEXT: cmp x1, x3
-; CHECK-GI-NEXT: csel w9, w10, w9, eq
+; CHECK-GI-NEXT: cset w10, lt
+; CHECK-GI-NEXT: csel w9, w9, w10, eq
; CHECK-GI-NEXT: tst w9, #0x1
; CHECK-GI-NEXT: csinv w0, w8, wzr, eq
; CHECK-GI-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/ucmp.ll b/llvm/test/CodeGen/AArch64/ucmp.ll
index 125ac7f61a41e5..0e4da89fcaebc5 100644
--- a/llvm/test/CodeGen/AArch64/ucmp.ll
+++ b/llvm/test/CodeGen/AArch64/ucmp.ll
@@ -79,20 +79,18 @@ define i8 @ucmp.8.128(i128 %x, i128 %y) nounwind {
;
; CHECK-GI-LABEL: ucmp.8.128:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: cmp x1, x3
-; CHECK-GI-NEXT: cset w8, hi
; CHECK-GI-NEXT: cmp x0, x2
-; CHECK-GI-NEXT: cset w9, hi
+; CHECK-GI-NEXT: cset w8, hi
; CHECK-GI-NEXT: cmp x1, x3
-; CHECK-GI-NEXT: csel w8, w9, w8, eq
+; CHECK-GI-NEXT: cset w9, hi
+; CHECK-GI-NEXT: csel w8, w8, w9, eq
; CHECK-GI-NEXT: tst w8, #0x1
; CHECK-GI-NEXT: cset w8, ne
-; CHECK-GI-NEXT: cmp x1, x3
-; CHECK-GI-NEXT: cset w9, lo
; CHECK-GI-NEXT: cmp x0, x2
-; CHECK-GI-NEXT: cset w10, lo
+; CHECK-GI-NEXT: cset w9, lo
; CHECK-GI-NEXT: cmp x1, x3
-; CHECK-GI-NEXT: csel w9, w10, w9, eq
+; CHECK-GI-NEXT: cset w10, lo
+; CHECK-GI-NEXT: csel w9, w9, w10, eq
; CHECK-GI-NEXT: tst w9, #0x1
; CHECK-GI-NEXT: csinv w0, w8, wzr, eq
; CHECK-GI-NEXT: ret
@@ -151,20 +149,18 @@ define <1 x i64> @ucmp.1.64.65(<1 x i65> %x, <1 x i65> %y) {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: and x8, x1, #0x1
; CHECK-GI-NEXT: and x9, x3, #0x1
-; CHECK-GI-NEXT: cmp x8, x9
-; CHECK-GI-NEXT: cset w10, hi
; CHECK-GI-NEXT: cmp x0, x2
-; CHECK-GI-NEXT: cset w11, hi
+; CHECK-GI-NEXT: cset w10, hi
; CHECK-GI-NEXT: cmp x8, x9
-; CHECK-GI-NEXT: csel w10, w11, w10, eq
+; CHECK-GI-NEXT: cset w11, hi
+; CHECK-GI-NEXT: csel w10, w10, w11, eq
; CHECK-GI-NEXT: tst w10, #0x1
; CHECK-GI-NEXT: cset x10, ne
-; CHECK-GI-NEXT: cmp x8, x9
-; CHECK-GI-NEXT: cset w11, lo
; CHECK-GI-NEXT: cmp x0, x2
-; CHECK-GI-NEXT: cset w12, lo
+; CHECK-GI-NEXT: cset w11, lo
; CHECK-GI-NEXT: cmp x8, x9
-; CHECK-GI-NEXT: csel w8, w12, w11, eq
+; CHECK-GI-NEXT: cset w8, lo
+; CHECK-GI-NEXT: csel w8, w11, w8, eq
; CHECK-GI-NEXT: tst w8, #0x1
; CHECK-GI-NEXT: csinv x8, x10, xzr, eq
; CHECK-GI-NEXT: fmov d0, x8
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll b/llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
index 809a6d6556a7be..0806f7da5c89ca 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
@@ -280,12 +280,11 @@ define i128 @test_v2i128(<2 x i128> %a) nounwind {
;
; CHECK-GI-LABEL: test_v2i128:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: cmp x1, x3
-; CHECK-GI-NEXT: cset w8, hi
; CHECK-GI-NEXT: cmp x0, x2
-; CHECK-GI-NEXT: cset w9, hi
+; CHECK-GI-NEXT: cset w8, hi
; CHECK-GI-NEXT: cmp x1, x3
-; CHECK-GI-NEXT: csel w8, w9, w8, eq
+; CHECK-GI-NEXT: cset w9, hi
+; CHECK-GI-NEXT: csel w8, w8, w9, eq
; CHECK-GI-NEXT: tst w8, #0x1
; CHECK-GI-NEXT: csel x0, x0, x2, ne
; CHECK-GI-NEXT: csel x1, x1, x3, ne
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
index 168e6dfa5f147d..e289ee759da158 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
@@ -5105,30 +5105,30 @@ define amdgpu_ps i128 @s_saddsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX6-LABEL: s_saddsat_i128:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_add_u32 s4, s0, s4
-; GFX6-NEXT: v_mov_b32_e32 v3, s1
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: s_addc_u32 s5, s1, s5
-; GFX6-NEXT: v_mov_b32_e32 v2, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: s_addc_u32 s8, s2, s6
-; GFX6-NEXT: v_mov_b32_e32 v0, s2
-; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[2:3]
+; GFX6-NEXT: v_mov_b32_e32 v2, s2
+; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1]
; GFX6-NEXT: s_addc_u32 s9, s3, s7
-; GFX6-NEXT: v_mov_b32_e32 v1, s3
-; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[0:1]
+; GFX6-NEXT: v_mov_b32_e32 v3, s3
+; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[2:3]
; GFX6-NEXT: v_cmp_lt_i64_e64 s[0:1], s[6:7], 0
-; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[0:1]
+; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[2:3]
+; GFX6-NEXT: v_mov_b32_e32 v2, s4
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX6-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], 0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
+; GFX6-NEXT: v_mov_b32_e32 v3, s5
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1]
; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX6-NEXT: s_ashr_i32 s0, s9, 31
; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
; GFX6-NEXT: s_add_i32 s1, s0, 0x80000000
; GFX6-NEXT: v_mov_b32_e32 v1, s0
-; GFX6-NEXT: v_mov_b32_e32 v2, s4
-; GFX6-NEXT: v_mov_b32_e32 v3, s5
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v2, v3, v1, vcc
@@ -5147,27 +5147,27 @@ define amdgpu_ps i128 @s_saddsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_add_u32 s4, s0, s4
; GFX8-NEXT: s_addc_u32 s5, s1, s5
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: s_addc_u32 s8, s2, s6
-; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: s_addc_u32 s9, s3, s7
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
-; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: s_cmp_eq_u64 s[8:9], s[2:3]
-; GFX8-NEXT: s_cselect_b32 s2, 1, 0
-; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[0:1]
-; GFX8-NEXT: s_and_b32 s0, 1, s2
+; GFX8-NEXT: s_cselect_b32 s0, 1, 0
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[2:3]
+; GFX8-NEXT: s_and_b32 s0, 1, s0
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX8-NEXT: s_cmp_eq_u64 s[6:7], 0
; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], s[6:7], 0
; GFX8-NEXT: s_cselect_b32 s2, 1, 0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX8-NEXT: s_and_b32 s0, 1, s2
; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1]
; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX8-NEXT: s_ashr_i32 s0, s9, 31
@@ -5194,27 +5194,27 @@ define amdgpu_ps i128 @s_saddsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_add_u32 s4, s0, s4
; GFX9-NEXT: s_addc_u32 s5, s1, s5
-; GFX9-NEXT: v_mov_b32_e32 v3, s1
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: s_addc_u32 s8, s2, s6
-; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: s_addc_u32 s9, s3, s7
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[2:3]
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: v_mov_b32_e32 v2, s2
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NEXT: s_cmp_eq_u64 s[8:9], s[2:3]
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[0:1]
-; GFX9-NEXT: s_and_b32 s0, 1, s2
+; GFX9-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[2:3]
+; GFX9-NEXT: s_and_b32 s0, 1, s0
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX9-NEXT: s_cmp_eq_u64 s[6:7], 0
; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], s[6:7], 0
; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX9-NEXT: s_and_b32 s0, 1, s2
; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1]
; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX9-NEXT: s_ashr_i32 s0, s9, 31
@@ -5895,30 +5895,30 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX6-LABEL: s_saddsat_v2i128:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_add_u32 s8, s0, s8
-; GFX6-NEXT: v_mov_b32_e32 v3, s1
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: s_addc_u32 s9, s1, s9
-; GFX6-NEXT: v_mov_b32_e32 v2, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: s_addc_u32 s16, s2, s10
-; GFX6-NEXT: v_mov_b32_e32 v0, s2
-; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[2:3]
+; GFX6-NEXT: v_mov_b32_e32 v2, s2
+; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
; GFX6-NEXT: s_addc_u32 s17, s3, s11
-; GFX6-NEXT: v_mov_b32_e32 v1, s3
-; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[16:17], v[0:1]
+; GFX6-NEXT: v_mov_b32_e32 v3, s3
+; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[16:17], v[2:3]
; GFX6-NEXT: v_cmp_lt_i64_e64 s[0:1], s[10:11], 0
-; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[16:17], v[0:1]
+; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[16:17], v[2:3]
+; GFX6-NEXT: v_mov_b32_e32 v2, s8
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX6-NEXT: v_cmp_eq_u64_e64 s[0:1], s[10:11], 0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
+; GFX6-NEXT: v_mov_b32_e32 v3, s9
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1]
; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX6-NEXT: s_ashr_i32 s0, s17, 31
; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
; GFX6-NEXT: s_add_i32 s1, s0, 0x80000000
; GFX6-NEXT: v_mov_b32_e32 v1, s0
-; GFX6-NEXT: v_mov_b32_e32 v2, s8
-; GFX6-NEXT: v_mov_b32_e32 v3, s9
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v4, v2, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc
@@ -5928,30 +5928,30 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX6-NEXT: v_cndmask_b32_e32 v6, v2, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v7, v3, v0, vcc
; GFX6-NEXT: s_add_u32 s0, s4, s12
-; GFX6-NEXT: v_mov_b32_e32 v2, s4
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: s_addc_u32 s1, s5, s13
-; GFX6-NEXT: v_mov_b32_e32 v3, s5
+; GFX6-NEXT: v_mov_b32_e32 v1, s5
; GFX6-NEXT: s_addc_u32 s2, s6, s14
-; GFX6-NEXT: v_mov_b32_e32 v0, s6
-; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[2:3]
+; GFX6-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]
; GFX6-NEXT: s_addc_u32 s3, s7, s15
-; GFX6-NEXT: v_mov_b32_e32 v1, s7
-; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
+; GFX6-NEXT: v_mov_b32_e32 v3, s7
+; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[2:3]
; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], s[14:15], 0
-; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[0:1]
+; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[2:3]
+; GFX6-NEXT: v_mov_b32_e32 v2, s0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; GFX6-NEXT: v_cmp_eq_u64_e64 s[4:5], s[14:15], 0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
+; GFX6-NEXT: v_mov_b32_e32 v3, s1
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]
; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX6-NEXT: s_ashr_i32 s4, s3, 31
; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
; GFX6-NEXT: s_add_i32 s5, s4, 0x80000000
; GFX6-NEXT: v_mov_b32_e32 v1, s4
-; GFX6-NEXT: v_mov_b32_e32 v2, s0
-; GFX6-NEXT: v_mov_b32_e32 v3, s1
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v2, v3, v1, vcc
@@ -5974,27 +5974,27 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX8: ; %bb.0:
; GFX8-NEXT: s_add_u32 s8, s0, s8
; GFX8-NEXT: s_addc_u32 s9, s1, s9
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: s_addc_u32 s16, s2, s10
-; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: s_addc_u32 s17, s3, s11
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
-; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: s_cmp_eq_u64 s[16:17], s[2:3]
-; GFX8-NEXT: s_cselect_b32 s2, 1, 0
-; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[16:17], v[0:1]
-; GFX8-NEXT: s_and_b32 s0, 1, s2
+; GFX8-NEXT: s_cselect_b32 s0, 1, 0
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[16:17], v[2:3]
+; GFX8-NEXT: s_and_b32 s0, 1, s0
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX8-NEXT: s_cmp_eq_u64 s[10:11], 0
; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], s[10:11], 0
; GFX8-NEXT: s_cselect_b32 s2, 1, 0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX8-NEXT: s_and_b32 s0, 1, s2
; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1]
; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX8-NEXT: s_ashr_i32 s0, s17, 31
@@ -6013,27 +6013,27 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX8-NEXT: v_cndmask_b32_e32 v6, v2, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v7, v3, v0, vcc
; GFX8-NEXT: s_addc_u32 s1, s5, s13
-; GFX8-NEXT: v_mov_b32_e32 v2, s4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_addc_u32 s2, s6, s14
-; GFX8-NEXT: v_mov_b32_e32 v3, s5
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s3, s7, s15
-; GFX8-NEXT: v_mov_b32_e32 v0, s6
-; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v1, s7
+; GFX8-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v3, s7
; GFX8-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]
-; GFX8-NEXT: s_cselect_b32 s6, 1, 0
-; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
-; GFX8-NEXT: s_and_b32 s4, 1, s6
+; GFX8-NEXT: s_cselect_b32 s4, 1, 0
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[2:3]
+; GFX8-NEXT: s_and_b32 s4, 1, s4
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX8-NEXT: s_cmp_eq_u64 s[14:15], 0
; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], s[14:15], 0
; GFX8-NEXT: s_cselect_b32 s6, 1, 0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; GFX8-NEXT: s_and_b32 s4, 1, s6
; GFX8-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]
; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX8-NEXT: s_ashr_i32 s4, s3, 31
@@ -6064,27 +6064,27 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX9: ; %bb.0:
; GFX9-NEXT: s_add_u32 s8, s0, s8
; GFX9-NEXT: s_addc_u32 s9, s1, s9
-; GFX9-NEXT: v_mov_b32_e32 v3, s1
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: s_addc_u32 s16, s2, s10
-; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: s_addc_u32 s17, s3, s11
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[2:3]
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: v_mov_b32_e32 v2, s2
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NEXT: s_cmp_eq_u64 s[16:17], s[2:3]
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[16:17], v[0:1]
-; GFX9-NEXT: s_and_b32 s0, 1, s2
+; GFX9-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[16:17], v[2:3]
+; GFX9-NEXT: s_and_b32 s0, 1, s0
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX9-NEXT: s_cmp_eq_u64 s[10:11], 0
; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], s[10:11], 0
; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX9-NEXT: s_and_b32 s0, 1, s2
; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1]
; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX9-NEXT: s_ashr_i32 s0, s17, 31
@@ -6103,27 +6103,27 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX9-NEXT: v_cndmask_b32_e32 v6, v2, v1, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v7, v3, v0, vcc
; GFX9-NEXT: s_addc_u32 s1, s5, s13
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: s_addc_u32 s2, s6, s14
-; GFX9-NEXT: v_mov_b32_e32 v3, s5
+; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: s_addc_u32 s3, s7, s15
-; GFX9-NEXT: v_mov_b32_e32 v0, s6
-; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[2:3]
-; GFX9-NEXT: v_mov_b32_e32 v1, s7
+; GFX9-NEXT: v_mov_b32_e32 v2, s6
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v3, s7
; GFX9-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]
-; GFX9-NEXT: s_cselect_b32 s6, 1, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
-; GFX9-NEXT: s_and_b32 s4, 1, s6
+; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[2:3]
+; GFX9-NEXT: s_and_b32 s4, 1, s4
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX9-NEXT: s_cmp_eq_u64 s[14:15], 0
; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], s[14:15], 0
; GFX9-NEXT: s_cselect_b32 s6, 1, 0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; GFX9-NEXT: s_and_b32 s4, 1, s6
; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]
; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX9-NEXT: s_ashr_i32 s4, s3, 31
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
index 7214f4ab581d5d..43ebe156eb2a28 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
@@ -5111,22 +5111,23 @@ define amdgpu_ps i128 @s_ssubsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX6-LABEL: s_ssubsat_i128:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_sub_u32 s8, s0, s4
-; GFX6-NEXT: v_mov_b32_e32 v3, s1
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: s_subb_u32 s9, s1, s5
-; GFX6-NEXT: v_mov_b32_e32 v2, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: s_subb_u32 s10, s2, s6
-; GFX6-NEXT: v_mov_b32_e32 v0, s2
-; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[2:3]
+; GFX6-NEXT: v_mov_b32_e32 v2, s2
+; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
; GFX6-NEXT: s_subb_u32 s11, s3, s7
-; GFX6-NEXT: v_mov_b32_e32 v1, s3
-; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[0:1]
+; GFX6-NEXT: v_mov_b32_e32 v3, s3
+; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[2:3]
; GFX6-NEXT: v_cmp_gt_u64_e64 s[0:1], s[4:5], 0
-; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[10:11], v[0:1]
+; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[10:11], v[2:3]
+; GFX6-NEXT: v_mov_b32_e32 v3, s9
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[6:7], 0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[6:7], 0
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
@@ -5136,7 +5137,6 @@ define amdgpu_ps i128 @s_ssubsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX6-NEXT: s_add_i32 s1, s0, 0x80000000
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: v_mov_b32_e32 v2, s8
-; GFX6-NEXT: v_mov_b32_e32 v3, s9
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v2, v3, v1, vcc
@@ -5155,26 +5155,26 @@ define amdgpu_ps i128 @s_ssubsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_sub_u32 s8, s0, s4
; GFX8-NEXT: s_subb_u32 s9, s1, s5
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: s_subb_u32 s10, s2, s6
-; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: s_subb_u32 s11, s3, s7
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
-; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: s_cmp_eq_u64 s[10:11], s[2:3]
-; GFX8-NEXT: s_cselect_b32 s2, 1, 0
-; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[0:1]
-; GFX8-NEXT: s_and_b32 s0, 1, s2
+; GFX8-NEXT: s_cselect_b32 s0, 1, 0
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[2:3]
+; GFX8-NEXT: s_and_b32 s0, 1, s0
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX8-NEXT: v_cmp_gt_u64_e64 s[0:1], s[4:5], 0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT: s_cmp_eq_u64 s[6:7], 0
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[6:7], 0
; GFX8-NEXT: s_cselect_b32 s2, 1, 0
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX8-NEXT: s_and_b32 s0, 1, s2
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
@@ -5204,26 +5204,26 @@ define amdgpu_ps i128 @s_ssubsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_sub_u32 s8, s0, s4
; GFX9-NEXT: s_subb_u32 s9, s1, s5
-; GFX9-NEXT: v_mov_b32_e32 v3, s1
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: s_subb_u32 s10, s2, s6
-; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: s_subb_u32 s11, s3, s7
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[2:3]
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: v_mov_b32_e32 v2, s2
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NEXT: s_cmp_eq_u64 s[10:11], s[2:3]
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[0:1]
-; GFX9-NEXT: s_and_b32 s0, 1, s2
+; GFX9-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[2:3]
+; GFX9-NEXT: s_and_b32 s0, 1, s0
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX9-NEXT: v_cmp_gt_u64_e64 s[0:1], s[4:5], 0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: s_cmp_eq_u64 s[6:7], 0
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[6:7], 0
; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX9-NEXT: s_and_b32 s0, 1, s2
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
@@ -5949,22 +5949,23 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX6-LABEL: s_ssubsat_v2i128:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_sub_u32 s16, s0, s8
-; GFX6-NEXT: v_mov_b32_e32 v3, s1
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: s_subb_u32 s17, s1, s9
-; GFX6-NEXT: v_mov_b32_e32 v2, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: s_subb_u32 s18, s2, s10
-; GFX6-NEXT: v_mov_b32_e32 v0, s2
-; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[16:17], v[2:3]
+; GFX6-NEXT: v_mov_b32_e32 v2, s2
+; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[16:17], v[0:1]
; GFX6-NEXT: s_subb_u32 s19, s3, s11
-; GFX6-NEXT: v_mov_b32_e32 v1, s3
-; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[18:19], v[0:1]
+; GFX6-NEXT: v_mov_b32_e32 v3, s3
+; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[18:19], v[2:3]
; GFX6-NEXT: v_cmp_gt_u64_e64 s[0:1], s[8:9], 0
-; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[18:19], v[0:1]
+; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[18:19], v[2:3]
+; GFX6-NEXT: v_mov_b32_e32 v3, s17
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[10:11], 0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[10:11], 0
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
@@ -5974,7 +5975,6 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX6-NEXT: s_add_i32 s1, s0, 0x80000000
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: v_mov_b32_e32 v2, s16
-; GFX6-NEXT: v_mov_b32_e32 v3, s17
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v4, v2, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc
@@ -5984,22 +5984,23 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX6-NEXT: v_cndmask_b32_e32 v6, v2, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v7, v3, v0, vcc
; GFX6-NEXT: s_sub_u32 s0, s4, s12
-; GFX6-NEXT: v_mov_b32_e32 v2, s4
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: s_subb_u32 s1, s5, s13
-; GFX6-NEXT: v_mov_b32_e32 v3, s5
+; GFX6-NEXT: v_mov_b32_e32 v1, s5
; GFX6-NEXT: s_subb_u32 s2, s6, s14
-; GFX6-NEXT: v_mov_b32_e32 v0, s6
-; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[2:3]
+; GFX6-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]
; GFX6-NEXT: s_subb_u32 s3, s7, s15
-; GFX6-NEXT: v_mov_b32_e32 v1, s7
-; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
+; GFX6-NEXT: v_mov_b32_e32 v3, s7
+; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[2:3]
; GFX6-NEXT: v_cmp_gt_u64_e64 s[4:5], s[12:13], 0
-; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[0:1]
+; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[2:3]
+; GFX6-NEXT: v_mov_b32_e32 v3, s1
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; GFX6-NEXT: v_cmp_gt_i64_e64 s[4:5], s[14:15], 0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[14:15], 0
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
@@ -6009,7 +6010,6 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX6-NEXT: s_add_i32 s5, s4, 0x80000000
; GFX6-NEXT: v_mov_b32_e32 v1, s4
; GFX6-NEXT: v_mov_b32_e32 v2, s0
-; GFX6-NEXT: v_mov_b32_e32 v3, s1
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v2, v3, v1, vcc
@@ -6032,26 +6032,26 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX8: ; %bb.0:
; GFX8-NEXT: s_sub_u32 s16, s0, s8
; GFX8-NEXT: s_subb_u32 s17, s1, s9
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: s_subb_u32 s18, s2, s10
-; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: s_subb_u32 s19, s3, s11
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
-; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[16:17], v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[16:17], v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: s_cmp_eq_u64 s[18:19], s[2:3]
-; GFX8-NEXT: s_cselect_b32 s2, 1, 0
-; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[18:19], v[0:1]
-; GFX8-NEXT: s_and_b32 s0, 1, s2
+; GFX8-NEXT: s_cselect_b32 s0, 1, 0
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[18:19], v[2:3]
+; GFX8-NEXT: s_and_b32 s0, 1, s0
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX8-NEXT: v_cmp_gt_u64_e64 s[0:1], s[8:9], 0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT: s_cmp_eq_u64 s[10:11], 0
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[10:11], 0
; GFX8-NEXT: s_cselect_b32 s2, 1, 0
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX8-NEXT: s_and_b32 s0, 1, s2
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
@@ -6073,26 +6073,26 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX8-NEXT: v_cndmask_b32_e32 v6, v2, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v7, v3, v0, vcc
; GFX8-NEXT: s_subb_u32 s1, s5, s13
-; GFX8-NEXT: v_mov_b32_e32 v2, s4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_subb_u32 s2, s6, s14
-; GFX8-NEXT: v_mov_b32_e32 v3, s5
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_subb_u32 s3, s7, s15
-; GFX8-NEXT: v_mov_b32_e32 v0, s6
-; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v1, s7
+; GFX8-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v3, s7
; GFX8-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]
-; GFX8-NEXT: s_cselect_b32 s6, 1, 0
-; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
-; GFX8-NEXT: s_and_b32 s4, 1, s6
+; GFX8-NEXT: s_cselect_b32 s4, 1, 0
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[2:3]
+; GFX8-NEXT: s_and_b32 s4, 1, s4
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX8-NEXT: v_cmp_gt_u64_e64 s[4:5], s[12:13], 0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT: s_cmp_eq_u64 s[14:15], 0
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; GFX8-NEXT: v_cmp_gt_i64_e64 s[4:5], s[14:15], 0
; GFX8-NEXT: s_cselect_b32 s6, 1, 0
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
; GFX8-NEXT: s_and_b32 s4, 1, s6
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
@@ -6126,26 +6126,26 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX9: ; %bb.0:
; GFX9-NEXT: s_sub_u32 s16, s0, s8
; GFX9-NEXT: s_subb_u32 s17, s1, s9
-; GFX9-NEXT: v_mov_b32_e32 v3, s1
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: s_subb_u32 s18, s2, s10
-; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: s_subb_u32 s19, s3, s11
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[16:17], v[2:3]
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: v_mov_b32_e32 v2, s2
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[16:17], v[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NEXT: s_cmp_eq_u64 s[18:19], s[2:3]
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[18:19], v[0:1]
-; GFX9-NEXT: s_and_b32 s0, 1, s2
+; GFX9-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[18:19], v[2:3]
+; GFX9-NEXT: s_and_b32 s0, 1, s0
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX9-NEXT: v_cmp_gt_u64_e64 s[0:1], s[8:9], 0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: s_cmp_eq_u64 s[10:11], 0
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[10:11], 0
; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX9-NEXT: s_and_b32 s0, 1, s2
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
@@ -6167,26 +6167,26 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX9-NEXT: v_cndmask_b32_e32 v6, v2, v1, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v7, v3, v0, vcc
; GFX9-NEXT: s_subb_u32 s1, s5, s13
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: s_subb_u32 s2, s6, s14
-; GFX9-NEXT: v_mov_b32_e32 v3, s5
+; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: s_subb_u32 s3, s7, s15
-; GFX9-NEXT: v_mov_b32_e32 v0, s6
-; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[2:3]
-; GFX9-NEXT: v_mov_b32_e32 v1, s7
+; GFX9-NEXT: v_mov_b32_e32 v2, s6
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v3, s7
; GFX9-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]
-; GFX9-NEXT: s_cselect_b32 s6, 1, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
-; GFX9-NEXT: s_and_b32 s4, 1, s6
+; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[2:3]
+; GFX9-NEXT: s_and_b32 s4, 1, s4
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX9-NEXT: v_cmp_gt_u64_e64 s[4:5], s[12:13], 0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: s_cmp_eq_u64 s[14:15], 0
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; GFX9-NEXT: v_cmp_gt_i64_e64 s[4:5], s[14:15], 0
; GFX9-NEXT: s_cselect_b32 s6, 1, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
; GFX9-NEXT: s_and_b32 s4, 1, s6
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
@@ -6300,15 +6300,15 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
;
; GFX11-LABEL: s_ssubsat_v2i128:
; GFX11: ; %bb.0:
-; GFX11-NEXT: s_sub_u32 s16, s0, s8
-; GFX11-NEXT: s_subb_u32 s17, s1, s9
-; GFX11-NEXT: s_subb_u32 s18, s2, s10
-; GFX11-NEXT: v_cmp_lt_u64_e64 s0, s[16:17], s[0:1]
-; GFX11-NEXT: s_subb_u32 s19, s3, s11
-; GFX11-NEXT: s_cmp_eq_u64 s[18:19], s[2:3]
+; GFX11-NEXT: s_sub_u32 s18, s0, s8
+; GFX11-NEXT: s_subb_u32 s19, s1, s9
+; GFX11-NEXT: s_subb_u32 s16, s2, s10
+; GFX11-NEXT: v_cmp_lt_u64_e64 s0, s[18:19], s[0:1]
+; GFX11-NEXT: s_subb_u32 s17, s3, s11
+; GFX11-NEXT: s_cmp_eq_u64 s[16:17], s[2:3]
; GFX11-NEXT: s_cselect_b32 s20, 1, 0
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: v_cmp_lt_i64_e64 s0, s[18:19], s[2:3]
+; GFX11-NEXT: v_cmp_lt_i64_e64 s0, s[16:17], s[2:3]
; GFX11-NEXT: v_cmp_gt_u64_e64 s2, s[8:9], 0
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
; GFX11-NEXT: s_and_b32 s0, 1, s20
@@ -6317,7 +6317,7 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX11-NEXT: v_cmp_gt_i64_e64 s2, s[10:11], 0
; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; GFX11-NEXT: s_cselect_b32 s1, 1, 0
-; GFX11-NEXT: s_ashr_i32 s8, s19, 31
+; GFX11-NEXT: s_ashr_i32 s8, s17, 31
; GFX11-NEXT: s_and_b32 s1, 1, s1
; GFX11-NEXT: s_add_i32 s9, s8, 0x80000000
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, s2
@@ -6351,12 +6351,12 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, s6
; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5
; GFX11-NEXT: s_add_i32 s0, s4, 0x80000000
-; GFX11-NEXT: v_dual_cndmask_b32 v2, v4, v3 :: v_dual_mov_b32 v3, s16
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v4, v3 :: v_dual_mov_b32 v3, s18
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT: v_mov_b32_e32 v0, s18
+; GFX11-NEXT: v_mov_b32_e32 v0, s16
; GFX11-NEXT: v_xor_b32_e32 v1, v2, v1
-; GFX11-NEXT: v_mov_b32_e32 v4, s17
-; GFX11-NEXT: v_mov_b32_e32 v2, s19
+; GFX11-NEXT: v_mov_b32_e32 v4, s19
+; GFX11-NEXT: v_mov_b32_e32 v2, s17
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s8, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s8, vcc_lo
; GFX11-NEXT: v_and_b32_e32 v1, 1, v1
diff --git a/llvm/test/CodeGen/AMDGPU/div_i128.ll b/llvm/test/CodeGen/AMDGPU/div_i128.ll
index b2f178c6c1041e..d9182d7ace8bfe 100644
--- a/llvm/test/CodeGen/AMDGPU/div_i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/div_i128.ll
@@ -1455,7 +1455,7 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: v_mov_b32_e32 v14, v0
; GFX9-G-O0-NEXT: v_mov_b32_e32 v15, v7
; GFX9-G-O0-NEXT: s_mov_b64 s[4:5], 0
-; GFX9-G-O0-NEXT: s_mov_b64 s[12:13], 0x7f
+; GFX9-G-O0-NEXT: s_mov_b64 s[8:9], 0x7f
; GFX9-G-O0-NEXT: ; kill: def $vgpr0_vgpr1 killed $vgpr3_vgpr4 killed $exec
; GFX9-G-O0-NEXT: s_waitcnt vmcnt(0)
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v5
@@ -1544,77 +1544,77 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: v_mov_b32_e32 v9, v10
; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, s5
; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, s4
-; GFX9-G-O0-NEXT: v_cmp_eq_u64_e64 s[8:9], v[8:9], v[10:11]
-; GFX9-G-O0-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
+; GFX9-G-O0-NEXT: v_cmp_eq_u64_e64 s[10:11], v[8:9], v[10:11]
+; GFX9-G-O0-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
; GFX9-G-O0-NEXT: v_mov_b32_e32 v8, v6
; GFX9-G-O0-NEXT: v_mov_b32_e32 v9, v3
; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, s5
; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, s4
-; GFX9-G-O0-NEXT: v_cmp_eq_u64_e64 s[8:9], v[8:9], v[10:11]
+; GFX9-G-O0-NEXT: v_cmp_eq_u64_e64 s[10:11], v[8:9], v[10:11]
; GFX9-G-O0-NEXT: v_ffbh_u32_e64 v4, v4
; GFX9-G-O0-NEXT: v_ffbh_u32_e64 v7, v7
; GFX9-G-O0-NEXT: v_mov_b32_e32 v8, 32
; GFX9-G-O0-NEXT: v_add_u32_e64 v7, v7, v8
; GFX9-G-O0-NEXT: v_min_u32_e64 v4, v4, v7
-; GFX9-G-O0-NEXT: s_mov_b32 s10, 64
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v7, s10
+; GFX9-G-O0-NEXT: s_mov_b32 s12, 64
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v7, s12
; GFX9-G-O0-NEXT: v_add_u32_e64 v4, v4, v7
; GFX9-G-O0-NEXT: v_ffbh_u32_e64 v3, v3
; GFX9-G-O0-NEXT: v_ffbh_u32_e64 v6, v6
; GFX9-G-O0-NEXT: v_mov_b32_e32 v7, 32
; GFX9-G-O0-NEXT: v_add_u32_e64 v6, v6, v7
; GFX9-G-O0-NEXT: v_min_u32_e64 v3, v3, v6
-; GFX9-G-O0-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[8:9]
+; GFX9-G-O0-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[10:11]
; GFX9-G-O0-NEXT: s_mov_b32 s16, 0
; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, v5
; GFX9-G-O0-NEXT: v_mov_b32_e32 v7, v2
; GFX9-G-O0-NEXT: v_mov_b32_e32 v9, s5
; GFX9-G-O0-NEXT: v_mov_b32_e32 v8, s4
-; GFX9-G-O0-NEXT: v_cmp_eq_u64_e64 s[8:9], v[6:7], v[8:9]
+; GFX9-G-O0-NEXT: v_cmp_eq_u64_e64 s[10:11], v[6:7], v[8:9]
; GFX9-G-O0-NEXT: v_ffbh_u32_e64 v4, v1
; GFX9-G-O0-NEXT: v_ffbh_u32_e64 v6, v0
; GFX9-G-O0-NEXT: v_mov_b32_e32 v7, 32
; GFX9-G-O0-NEXT: v_add_u32_e64 v6, v6, v7
; GFX9-G-O0-NEXT: v_min_u32_e64 v4, v4, v6
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, s10
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, s12
; GFX9-G-O0-NEXT: v_add_u32_e64 v6, v4, v6
; GFX9-G-O0-NEXT: v_ffbh_u32_e64 v4, v2
; GFX9-G-O0-NEXT: v_ffbh_u32_e64 v7, v5
; GFX9-G-O0-NEXT: v_mov_b32_e32 v8, 32
; GFX9-G-O0-NEXT: v_add_u32_e64 v7, v7, v8
; GFX9-G-O0-NEXT: v_min_u32_e64 v4, v4, v7
-; GFX9-G-O0-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[8:9]
+; GFX9-G-O0-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[10:11]
; GFX9-G-O0-NEXT: s_mov_b32 s15, 0
-; GFX9-G-O0-NEXT: s_mov_b32 s11, 0
+; GFX9-G-O0-NEXT: s_mov_b32 s13, 0
; GFX9-G-O0-NEXT: s_mov_b32 s14, 0
-; GFX9-G-O0-NEXT: s_mov_b32 s10, 0
-; GFX9-G-O0-NEXT: v_sub_co_u32_e64 v6, s[8:9], v3, v4
+; GFX9-G-O0-NEXT: s_mov_b32 s12, 0
+; GFX9-G-O0-NEXT: v_sub_co_u32_e64 v6, s[10:11], v3, v4
; GFX9-G-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, s16
; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, s16
-; GFX9-G-O0-NEXT: v_subb_co_u32_e64 v3, s[8:9], v3, v4, s[8:9]
+; GFX9-G-O0-NEXT: v_subb_co_u32_e64 v3, s[10:11], v3, v4, s[10:11]
; GFX9-G-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, s15
; GFX9-G-O0-NEXT: v_mov_b32_e32 v7, s14
-; GFX9-G-O0-NEXT: v_subb_co_u32_e64 v8, s[8:9], v4, v7, s[8:9]
+; GFX9-G-O0-NEXT: v_subb_co_u32_e64 v8, s[10:11], v4, v7, s[10:11]
; GFX9-G-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, s11
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v7, s10
-; GFX9-G-O0-NEXT: v_subb_co_u32_e64 v7, s[8:9], v4, v7, s[8:9]
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, s13
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v7, s12
+; GFX9-G-O0-NEXT: v_subb_co_u32_e64 v7, s[10:11], v4, v7, s[10:11]
; GFX9-G-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v9, v6
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, v3
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, v8
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v12, v7
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v14, s5
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v13, s4
-; GFX9-G-O0-NEXT: v_cmp_gt_u64_e64 s[10:11], v[11:12], v[13:14]
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v14, s5
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v13, s4
-; GFX9-G-O0-NEXT: v_cmp_eq_u64_e64 s[8:9], v[11:12], v[13:14]
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, s12
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v12, s13
-; GFX9-G-O0-NEXT: v_cmp_gt_u64_e64 s[12:13], v[9:10], v[11:12]
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, v6
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v12, v3
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v9, v8
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, v7
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v14, s9
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v13, s8
+; GFX9-G-O0-NEXT: v_cmp_gt_u64_e64 s[12:13], v[11:12], v[13:14]
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v12, s5
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, s4
+; GFX9-G-O0-NEXT: v_cmp_gt_u64_e64 s[10:11], v[9:10], v[11:12]
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v12, s5
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, s4
+; GFX9-G-O0-NEXT: v_cmp_eq_u64_e64 s[8:9], v[9:10], v[11:12]
; GFX9-G-O0-NEXT: v_mov_b32_e32 v9, 1
; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, 0
; GFX9-G-O0-NEXT: v_cndmask_b32_e64 v9, v4, v9, s[12:13]
@@ -3688,20 +3688,20 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: v_mov_b32_e32 v7, s10
; GFX9-G-O0-NEXT: v_subb_co_u32_e64 v7, s[8:9], v4, v7, s[8:9]
; GFX9-G-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-G-O0-NEXT: s_mov_b64 s[12:13], 0x7f
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v9, v5
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, v6
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, v8
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v12, v7
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v14, s5
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v13, s4
-; GFX9-G-O0-NEXT: v_cmp_gt_u64_e64 s[10:11], v[11:12], v[13:14]
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v14, s5
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v13, s4
-; GFX9-G-O0-NEXT: v_cmp_eq_u64_e64 s[8:9], v[11:12], v[13:14]
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, s12
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v12, s13
-; GFX9-G-O0-NEXT: v_cmp_gt_u64_e64 s[12:13], v[9:10], v[11:12]
+; GFX9-G-O0-NEXT: s_mov_b64 s[8:9], 0x7f
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, v5
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v12, v6
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v9, v8
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, v7
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v14, s9
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v13, s8
+; GFX9-G-O0-NEXT: v_cmp_gt_u64_e64 s[12:13], v[11:12], v[13:14]
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v12, s5
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, s4
+; GFX9-G-O0-NEXT: v_cmp_gt_u64_e64 s[10:11], v[9:10], v[11:12]
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v12, s5
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, s4
+; GFX9-G-O0-NEXT: v_cmp_eq_u64_e64 s[8:9], v[9:10], v[11:12]
; GFX9-G-O0-NEXT: v_mov_b32_e32 v9, 1
; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, 0
; GFX9-G-O0-NEXT: v_cndmask_b32_e64 v9, v4, v9, s[12:13]
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir
index 3c81427231a359..c3ccc820fc02bf 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir
@@ -209,10 +209,10 @@ body: |
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
+ ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
; MIPS32-NEXT: RetRA implicit $v0
%2:_(s32) = COPY $a0
@@ -242,10 +242,10 @@ body: |
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY2]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY2]]
+ ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
; MIPS32-NEXT: RetRA implicit $v0
%2:_(s32) = COPY $a0
@@ -275,10 +275,10 @@ body: |
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
+ ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
; MIPS32-NEXT: RetRA implicit $v0
%2:_(s32) = COPY $a0
@@ -308,10 +308,10 @@ body: |
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY]](s32), [[COPY2]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY]](s32), [[COPY2]]
+ ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
; MIPS32-NEXT: RetRA implicit $v0
%2:_(s32) = COPY $a0
@@ -341,10 +341,10 @@ body: |
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
+ ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
; MIPS32-NEXT: RetRA implicit $v0
%2:_(s32) = COPY $a0
@@ -374,10 +374,10 @@ body: |
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY2]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY2]]
+ ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
; MIPS32-NEXT: RetRA implicit $v0
%2:_(s32) = COPY $a0
@@ -407,10 +407,10 @@ body: |
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
+ ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
; MIPS32-NEXT: RetRA implicit $v0
%2:_(s32) = COPY $a0
@@ -440,10 +440,10 @@ body: |
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY]](s32), [[COPY2]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY]](s32), [[COPY2]]
+ ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
; MIPS32-NEXT: RetRA implicit $v0
%2:_(s32) = COPY $a0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll
index 49f2a78683b0a5..2f8d075bf766ab 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll
@@ -188,8 +188,8 @@ entry:
define i1 @sgt_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: sgt_i64:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: slt $2, $7, $5
; MIPS32-NEXT: sltu $1, $6, $4
+; MIPS32-NEXT: slt $2, $7, $5
; MIPS32-NEXT: xor $3, $5, $7
; MIPS32-NEXT: movz $2, $1, $3
; MIPS32-NEXT: jr $ra
@@ -202,10 +202,10 @@ entry:
define i1 @sge_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: sge_i64:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: slt $1, $5, $7
-; MIPS32-NEXT: xori $2, $1, 1
; MIPS32-NEXT: sltu $1, $4, $6
; MIPS32-NEXT: xori $1, $1, 1
+; MIPS32-NEXT: slt $2, $5, $7
+; MIPS32-NEXT: xori $2, $2, 1
; MIPS32-NEXT: xor $3, $5, $7
; MIPS32-NEXT: movz $2, $1, $3
; MIPS32-NEXT: jr $ra
@@ -218,8 +218,8 @@ entry:
define i1 @slt_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: slt_i64:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: slt $2, $5, $7
; MIPS32-NEXT: sltu $1, $4, $6
+; MIPS32-NEXT: slt $2, $5, $7
; MIPS32-NEXT: xor $3, $5, $7
; MIPS32-NEXT: movz $2, $1, $3
; MIPS32-NEXT: jr $ra
@@ -232,10 +232,10 @@ entry:
define i1 @sle_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: sle_i64:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: slt $1, $7, $5
-; MIPS32-NEXT: xori $2, $1, 1
; MIPS32-NEXT: sltu $1, $6, $4
; MIPS32-NEXT: xori $1, $1, 1
+; MIPS32-NEXT: slt $2, $7, $5
+; MIPS32-NEXT: xori $2, $2, 1
; MIPS32-NEXT: xor $3, $5, $7
; MIPS32-NEXT: movz $2, $1, $3
; MIPS32-NEXT: jr $ra
@@ -248,8 +248,8 @@ entry:
define i1 @ugt_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: ugt_i64:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: sltu $2, $7, $5
; MIPS32-NEXT: sltu $1, $6, $4
+; MIPS32-NEXT: sltu $2, $7, $5
; MIPS32-NEXT: xor $3, $5, $7
; MIPS32-NEXT: movz $2, $1, $3
; MIPS32-NEXT: jr $ra
@@ -262,10 +262,10 @@ entry:
define i1 @uge_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: uge_i64:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: sltu $1, $5, $7
-; MIPS32-NEXT: xori $2, $1, 1
; MIPS32-NEXT: sltu $1, $4, $6
; MIPS32-NEXT: xori $1, $1, 1
+; MIPS32-NEXT: sltu $2, $5, $7
+; MIPS32-NEXT: xori $2, $2, 1
; MIPS32-NEXT: xor $3, $5, $7
; MIPS32-NEXT: movz $2, $1, $3
; MIPS32-NEXT: jr $ra
@@ -278,8 +278,8 @@ entry:
define i1 @ult_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: ult_i64:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: sltu $2, $5, $7
; MIPS32-NEXT: sltu $1, $4, $6
+; MIPS32-NEXT: sltu $2, $5, $7
; MIPS32-NEXT: xor $3, $5, $7
; MIPS32-NEXT: movz $2, $1, $3
; MIPS32-NEXT: jr $ra
@@ -292,10 +292,10 @@ entry:
define i1 @ule_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: ule_i64:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: sltu $1, $7, $5
-; MIPS32-NEXT: xori $2, $1, 1
; MIPS32-NEXT: sltu $1, $6, $4
; MIPS32-NEXT: xori $1, $1, 1
+; MIPS32-NEXT: sltu $2, $7, $5
+; MIPS32-NEXT: xori $2, $2, 1
; MIPS32-NEXT: xor $3, $5, $7
; MIPS32-NEXT: movz $2, $1, $3
; MIPS32-NEXT: jr $ra
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv32.mir
index 3a292093aa6075..5288bb5e87011d 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv32.mir
@@ -121,14 +121,14 @@ body: |
; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32)
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY5]](s32), [[COPY1]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY5]](s32), [[COPY1]]
- ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY4]](s32), [[COPY]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP3]], [[ICMP1]]
- ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY3]](s32), [[C]]
- ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]]
- ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[C]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s32), [[ICMP6]], [[ICMP4]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY4]](s32), [[COPY]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY5]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY5]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[ICMP1]], [[ICMP2]]
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[C]]
+ ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY3]](s32), [[C]]
+ ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s32), [[ICMP4]], [[ICMP5]]
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SELECT1]], [[SELECT]]
; CHECK-NEXT: $x10 = COPY [[COPY4]](s32)
; CHECK-NEXT: $x11 = COPY [[COPY5]](s32)
@@ -266,14 +266,14 @@ body: |
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY3]]
; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[SUB2]](s32), [[COPY1]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB2]](s32), [[COPY1]]
- ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB]](s32), [[COPY]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP3]], [[ICMP1]]
- ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY3]](s32), [[C]]
- ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]]
- ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY2]](s32), [[C]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s32), [[ICMP6]], [[ICMP4]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB]](s32), [[COPY]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[SUB2]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB2]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[ICMP1]], [[ICMP2]]
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY2]](s32), [[C]]
+ ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY3]](s32), [[C]]
+ ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s32), [[ICMP4]], [[ICMP5]]
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SELECT1]], [[SELECT]]
; CHECK-NEXT: $x10 = COPY [[SUB]](s32)
; CHECK-NEXT: $x11 = COPY [[SUB2]](s32)
@@ -401,10 +401,10 @@ body: |
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY3]]
; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP]]
; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32)
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY5]](s32), [[COPY3]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY5]](s32), [[COPY3]]
- ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY4]](s32), [[COPY2]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP3]], [[ICMP1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY4]](s32), [[COPY2]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY5]](s32), [[COPY3]]
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY5]](s32), [[COPY3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[ICMP1]], [[ICMP2]]
; CHECK-NEXT: $x10 = COPY [[COPY4]](s32)
; CHECK-NEXT: $x11 = COPY [[COPY5]](s32)
; CHECK-NEXT: $x12 = COPY [[SELECT]](s32)
@@ -528,10 +528,10 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY3]]
; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY1]](s32), [[COPY3]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
- ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP3]], [[ICMP1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY1]](s32), [[COPY3]]
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[ICMP1]], [[ICMP2]]
; CHECK-NEXT: $x10 = COPY [[SUB]](s32)
; CHECK-NEXT: $x11 = COPY [[SUB2]](s32)
; CHECK-NEXT: $x12 = COPY [[SELECT]](s32)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv32.mir
index 413dbe275dfde5..8081cfbd7edabe 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv32.mir
@@ -108,10 +108,10 @@ body: |
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %ylo, [[C]](s32)
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[ASHR]](s32), [[ASHR1]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ASHR]](s32), [[ASHR1]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), %xhi(s32), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), %xhi(s32), %yhi
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[ASHR]](s32), [[ASHR1]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ASHR]](s32), [[ASHR1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -137,10 +137,10 @@ body: |
; CHECK-NEXT: %xlo:_(s32) = COPY $x11
; CHECK-NEXT: %yhi:_(s32) = COPY $x12
; CHECK-NEXT: %ylo:_(s32) = COPY $x13
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), %xlo(s32), %ylo
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), %xhi(s32), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), %xhi(s32), %yhi
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), %xlo(s32), %ylo
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -262,10 +262,10 @@ body: |
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %ylo, [[C]](s32)
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ASHR]](s32), [[ASHR1]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %xhi(s32), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %xhi(s32), %yhi
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ASHR]](s32), [[ASHR1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -291,10 +291,10 @@ body: |
; CHECK-NEXT: %xlo:_(s32) = COPY $x11
; CHECK-NEXT: %yhi:_(s32) = COPY $x12
; CHECK-NEXT: %ylo:_(s32) = COPY $x13
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), %xlo(s32), %ylo
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %xhi(s32), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %xhi(s32), %yhi
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), %xlo(s32), %ylo
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -416,10 +416,10 @@ body: |
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %ylo, [[C]](s32)
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[ASHR]](s32), [[ASHR1]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ASHR]](s32), [[ASHR1]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), %xhi(s32), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), %xhi(s32), %yhi
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[ASHR]](s32), [[ASHR1]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ASHR]](s32), [[ASHR1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -445,10 +445,10 @@ body: |
; CHECK-NEXT: %xlo:_(s32) = COPY $x11
; CHECK-NEXT: %yhi:_(s32) = COPY $x12
; CHECK-NEXT: %ylo:_(s32) = COPY $x13
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), %xlo(s32), %ylo
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), %xhi(s32), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), %xhi(s32), %yhi
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), %xlo(s32), %ylo
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -570,10 +570,10 @@ body: |
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %ylo, [[C]](s32)
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), [[ASHR]](s32), [[ASHR1]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ASHR]](s32), [[ASHR1]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), %xhi(s32), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), %xhi(s32), %yhi
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), [[ASHR]](s32), [[ASHR1]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ASHR]](s32), [[ASHR1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -599,10 +599,10 @@ body: |
; CHECK-NEXT: %xlo:_(s32) = COPY $x11
; CHECK-NEXT: %yhi:_(s32) = COPY $x12
; CHECK-NEXT: %ylo:_(s32) = COPY $x13
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), %xlo(s32), %ylo
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), %xhi(s32), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), %xhi(s32), %yhi
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), %xlo(s32), %ylo
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -719,10 +719,10 @@ body: |
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND %xlo, [[C1]]
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND %yhi, [[C]]
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND %ylo, [[C1]]
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND1]](s32), [[AND3]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND1]](s32), [[AND3]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[AND2]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[AND2]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND1]](s32), [[AND3]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND1]](s32), [[AND3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -748,10 +748,10 @@ body: |
; CHECK-NEXT: %xlo:_(s32) = COPY $x11
; CHECK-NEXT: %yhi:_(s32) = COPY $x12
; CHECK-NEXT: %ylo:_(s32) = COPY $x13
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), %xlo(s32), %ylo
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), %xhi(s32), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), %xhi(s32), %yhi
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), %xlo(s32), %ylo
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -868,10 +868,10 @@ body: |
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND %xlo, [[C1]]
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND %yhi, [[C]]
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND %ylo, [[C1]]
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND1]](s32), [[AND3]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND1]](s32), [[AND3]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND2]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND2]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND1]](s32), [[AND3]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND1]](s32), [[AND3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -897,10 +897,10 @@ body: |
; CHECK-NEXT: %xlo:_(s32) = COPY $x11
; CHECK-NEXT: %yhi:_(s32) = COPY $x12
; CHECK-NEXT: %ylo:_(s32) = COPY $x13
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), %xlo(s32), %ylo
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), %xhi(s32), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), %xhi(s32), %yhi
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), %xlo(s32), %ylo
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -1017,10 +1017,10 @@ body: |
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND %xlo, [[C1]]
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND %yhi, [[C]]
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND %ylo, [[C1]]
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[AND1]](s32), [[AND3]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND1]](s32), [[AND3]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[AND]](s32), [[AND2]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[AND]](s32), [[AND2]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[AND1]](s32), [[AND3]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND1]](s32), [[AND3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -1046,10 +1046,10 @@ body: |
; CHECK-NEXT: %xlo:_(s32) = COPY $x11
; CHECK-NEXT: %yhi:_(s32) = COPY $x12
; CHECK-NEXT: %ylo:_(s32) = COPY $x13
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), %xlo(s32), %ylo
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), %xhi(s32), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), %xhi(s32), %yhi
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), %xlo(s32), %ylo
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -1166,10 +1166,10 @@ body: |
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND %xlo, [[C1]]
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND %yhi, [[C]]
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND %ylo, [[C1]]
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[AND1]](s32), [[AND3]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND1]](s32), [[AND3]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[AND]](s32), [[AND2]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[AND]](s32), [[AND2]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[AND1]](s32), [[AND3]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND1]](s32), [[AND3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -1195,10 +1195,10 @@ body: |
; CHECK-NEXT: %xlo:_(s32) = COPY $x11
; CHECK-NEXT: %yhi:_(s32) = COPY $x12
; CHECK-NEXT: %ylo:_(s32) = COPY $x13
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), %xlo(s32), %ylo
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), %xhi(s32), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), %xhi(s32), %yhi
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), %xlo(s32), %ylo
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -1533,3 +1533,53 @@ body: |
PseudoRET implicit $x10
...
+---
+name: cmp_slt_i128
+body: |
+ bb.1:
+ liveins: $x10, $x11
+
+ ; CHECK-LABEL: name: cmp_slt_i128
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32), align 8)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s32)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s32) from unknown-address + 8, align 8)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s32)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from unknown-address + 12)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
+ ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load (s32), align 8)
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C]](s32)
+ ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p0) :: (load (s32) from unknown-address + 4)
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C1]](s32)
+ ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p0) :: (load (s32) from unknown-address + 8, align 8)
+ ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C2]](s32)
+ ; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p0) :: (load (s32) from unknown-address + 12)
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD]](s32), [[LOAD4]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD1]](s32), [[LOAD5]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[LOAD1]](s32), [[LOAD5]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD2]](s32), [[LOAD6]]
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[LOAD2]](s32), [[LOAD6]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s32), [[SELECT]], [[ICMP3]]
+ ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[LOAD3]](s32), [[LOAD7]]
+ ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[LOAD3]](s32), [[LOAD7]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s32), [[SELECT1]], [[ICMP5]]
+ ; CHECK-NEXT: $x10 = COPY [[SELECT2]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %2:_(p0) = COPY $x10
+ %0:_(s128) = G_LOAD %2(p0) :: (load (s128), align 8)
+ %3:_(p0) = COPY $x11
+ %1:_(s128) = G_LOAD %3(p0) :: (load (s128), align 8)
+ %4:_(s1) = G_ICMP intpred(slt), %0(s128), %1
+ %5:_(s32) = G_ANYEXT %4(s1)
+ $x10 = COPY %5(s32)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv64.mir
index 27ac60ae143131..74d745732d59d7 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv64.mir
@@ -130,12 +130,12 @@ body: |
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL %ylo, [[C]](s64)
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64)
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[ASHR]](s64), [[ASHR1]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ASHR]](s64), [[ASHR1]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), %xhi(s64), %yhi
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP2]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s64), [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), %xhi(s64), %yhi
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[ASHR]](s64), [[ASHR1]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ASHR]](s64), [[ASHR1]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32)
; CHECK-NEXT: $x10 = COPY %z0(s64)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -162,12 +162,12 @@ body: |
; CHECK-NEXT: %xlo:_(s64) = COPY $x11
; CHECK-NEXT: %yhi:_(s64) = COPY $x12
; CHECK-NEXT: %ylo:_(s64) = COPY $x13
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), %xlo(s64), %ylo
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), %xhi(s64), %yhi
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP2]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s64), [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), %xhi(s64), %yhi
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), %xlo(s64), %ylo
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32)
; CHECK-NEXT: $x10 = COPY %z0(s64)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -312,12 +312,12 @@ body: |
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL %ylo, [[C]](s64)
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64)
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), [[ASHR]](s64), [[ASHR1]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ASHR]](s64), [[ASHR1]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xhi(s64), %yhi
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP2]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s64), [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xhi(s64), %yhi
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), [[ASHR]](s64), [[ASHR1]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ASHR]](s64), [[ASHR1]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32)
; CHECK-NEXT: $x10 = COPY %z0(s64)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -344,12 +344,12 @@ body: |
; CHECK-NEXT: %xlo:_(s64) = COPY $x11
; CHECK-NEXT: %yhi:_(s64) = COPY $x12
; CHECK-NEXT: %ylo:_(s64) = COPY $x13
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), %xlo(s64), %ylo
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %xhi(s64), %yhi
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP2]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s64), [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %xhi(s64), %yhi
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), %xlo(s64), %ylo
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32)
; CHECK-NEXT: $x10 = COPY %z0(s64)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -494,12 +494,12 @@ body: |
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL %ylo, [[C]](s64)
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64)
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), [[ASHR]](s64), [[ASHR1]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ASHR]](s64), [[ASHR1]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xhi(s64), %yhi
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP2]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s64), [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xhi(s64), %yhi
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), [[ASHR]](s64), [[ASHR1]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ASHR]](s64), [[ASHR1]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32)
; CHECK-NEXT: $x10 = COPY %z0(s64)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -526,12 +526,12 @@ body: |
; CHECK-NEXT: %xlo:_(s64) = COPY $x11
; CHECK-NEXT: %yhi:_(s64) = COPY $x12
; CHECK-NEXT: %ylo:_(s64) = COPY $x13
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), %xlo(s64), %ylo
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xhi(s64), %yhi
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP2]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s64), [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xhi(s64), %yhi
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), %xlo(s64), %ylo
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32)
; CHECK-NEXT: $x10 = COPY %z0(s64)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -676,12 +676,12 @@ body: |
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL %ylo, [[C]](s64)
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64)
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sle), [[ASHR]](s64), [[ASHR1]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ASHR]](s64), [[ASHR1]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), %xhi(s64), %yhi
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP2]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s64), [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), %xhi(s64), %yhi
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(sle), [[ASHR]](s64), [[ASHR1]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ASHR]](s64), [[ASHR1]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32)
; CHECK-NEXT: $x10 = COPY %z0(s64)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -708,12 +708,12 @@ body: |
; CHECK-NEXT: %xlo:_(s64) = COPY $x11
; CHECK-NEXT: %yhi:_(s64) = COPY $x12
; CHECK-NEXT: %ylo:_(s64) = COPY $x13
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sle), %xlo(s64), %ylo
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), %xhi(s64), %yhi
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP2]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s64), [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), %xhi(s64), %yhi
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(sle), %xlo(s64), %ylo
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32)
; CHECK-NEXT: $x10 = COPY %z0(s64)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -854,12 +854,12 @@ body: |
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND %xlo, [[C1]]
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND %yhi, [[C]]
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND %ylo, [[C1]]
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[AND1]](s64), [[AND3]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[AND1]](s64), [[AND3]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[AND]](s64), [[AND2]]
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP2]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s64), [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[AND]](s64), [[AND2]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[AND1]](s64), [[AND3]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[AND1]](s64), [[AND3]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32)
; CHECK-NEXT: $x10 = COPY %z0(s64)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -886,12 +886,12 @@ body: |
; CHECK-NEXT: %xlo:_(s64) = COPY $x11
; CHECK-NEXT: %yhi:_(s64) = COPY $x12
; CHECK-NEXT: %ylo:_(s64) = COPY $x13
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), %xlo(s64), %ylo
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), %xhi(s64), %yhi
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP2]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s64), [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), %xhi(s64), %yhi
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), %xlo(s64), %ylo
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32)
; CHECK-NEXT: $x10 = COPY %z0(s64)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -1032,12 +1032,12 @@ body: |
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND %xlo, [[C1]]
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND %yhi, [[C]]
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND %ylo, [[C1]]
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[AND1]](s64), [[AND3]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[AND1]](s64), [[AND3]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[AND]](s64), [[AND2]]
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP2]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s64), [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[AND]](s64), [[AND2]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[AND1]](s64), [[AND3]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[AND1]](s64), [[AND3]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32)
; CHECK-NEXT: $x10 = COPY %z0(s64)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -1064,12 +1064,12 @@ body: |
; CHECK-NEXT: %xlo:_(s64) = COPY $x11
; CHECK-NEXT: %yhi:_(s64) = COPY $x12
; CHECK-NEXT: %ylo:_(s64) = COPY $x13
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), %xlo(s64), %ylo
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xhi(s64), %yhi
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP2]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s64), [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xhi(s64), %yhi
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), %xlo(s64), %ylo
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32)
; CHECK-NEXT: $x10 = COPY %z0(s64)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -1210,12 +1210,12 @@ body: |
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND %xlo, [[C1]]
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND %yhi, [[C]]
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND %ylo, [[C1]]
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), [[AND1]](s64), [[AND3]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[AND1]](s64), [[AND3]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), [[AND]](s64), [[AND2]]
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP2]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s64), [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), [[AND]](s64), [[AND2]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), [[AND1]](s64), [[AND3]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[AND1]](s64), [[AND3]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32)
; CHECK-NEXT: $x10 = COPY %z0(s64)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -1242,12 +1242,12 @@ body: |
; CHECK-NEXT: %xlo:_(s64) = COPY $x11
; CHECK-NEXT: %yhi:_(s64) = COPY $x12
; CHECK-NEXT: %ylo:_(s64) = COPY $x13
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xlo(s64), %ylo
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xhi(s64), %yhi
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP2]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s64), [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xhi(s64), %yhi
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xlo(s64), %ylo
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32)
; CHECK-NEXT: $x10 = COPY %z0(s64)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -1388,12 +1388,12 @@ body: |
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND %xlo, [[C1]]
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND %yhi, [[C]]
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND %ylo, [[C1]]
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), [[AND1]](s64), [[AND3]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[AND1]](s64), [[AND3]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), [[AND]](s64), [[AND2]]
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP2]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s64), [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), [[AND]](s64), [[AND2]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), [[AND1]](s64), [[AND3]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[AND1]](s64), [[AND3]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32)
; CHECK-NEXT: $x10 = COPY %z0(s64)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -1420,12 +1420,12 @@ body: |
; CHECK-NEXT: %xlo:_(s64) = COPY $x11
; CHECK-NEXT: %yhi:_(s64) = COPY $x12
; CHECK-NEXT: %ylo:_(s64) = COPY $x13
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), %xlo(s64), %ylo
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), %xhi(s64), %yhi
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP2]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s64), [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), %xhi(s64), %yhi
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), %xlo(s64), %ylo
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32)
; CHECK-NEXT: $x10 = COPY %z0(s64)
; CHECK-NEXT: PseudoRET implicit $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv32.mir
index 4932b1aebdec68..227a8cd7eb5ba6 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv32.mir
@@ -59,10 +59,10 @@ body: |
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY3]]
; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP]]
; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32)
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY5]](s32), [[COPY3]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY5]](s32), [[COPY3]]
- ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY4]](s32), [[COPY2]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP3]], [[ICMP1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY4]](s32), [[COPY2]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY5]](s32), [[COPY3]]
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY5]](s32), [[COPY3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[ICMP1]], [[ICMP2]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[C]], [[COPY4]]
; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[C]], [[COPY5]]
@@ -150,14 +150,14 @@ body: |
; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32)
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY5]](s32), [[COPY1]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY5]](s32), [[COPY1]]
- ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY4]](s32), [[COPY]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP3]], [[ICMP1]]
- ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY3]](s32), [[C]]
- ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]]
- ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[C]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s32), [[ICMP6]], [[ICMP4]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY4]](s32), [[COPY]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY5]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY5]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[ICMP1]], [[ICMP2]]
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[C]]
+ ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY3]](s32), [[C]]
+ ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s32), [[ICMP4]], [[ICMP5]]
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SELECT1]], [[SELECT]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY5]], [[C1]](s32)
@@ -237,10 +237,10 @@ body: |
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY3]]
; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY1]](s32), [[COPY3]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
- ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP3]], [[ICMP1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY1]](s32), [[COPY3]]
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[ICMP1]], [[ICMP2]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[C]], [[SUB]]
; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[C]], [[SUB2]]
; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32)
@@ -325,14 +325,14 @@ body: |
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY3]]
; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[SUB2]](s32), [[COPY1]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB2]](s32), [[COPY1]]
- ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB]](s32), [[COPY]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP3]], [[ICMP1]]
- ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY3]](s32), [[C]]
- ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]]
- ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY2]](s32), [[C]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s32), [[ICMP6]], [[ICMP4]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB]](s32), [[COPY]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[SUB2]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB2]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[ICMP1]], [[ICMP2]]
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY2]](s32), [[C]]
+ ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY3]](s32), [[C]]
+ ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s32), [[ICMP4]], [[ICMP5]]
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SELECT1]], [[SELECT]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SUB2]], [[C1]](s32)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smax-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smax-rv32.mir
index 6143755422f269..038d8e4b7f6c19 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smax-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smax-rv32.mir
@@ -111,10 +111,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY1]](s32), [[COPY3]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY1]](s32), [[COPY3]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[COPY]], [[COPY2]]
; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smin-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smin-rv32.mir
index bce8e25e9ceb1a..631b6eb49ef24f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smin-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smin-rv32.mir
@@ -111,10 +111,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY1]](s32), [[COPY3]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY1]](s32), [[COPY3]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[COPY]], [[COPY2]]
; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv32.mir
index fdb890a112e549..83ba02b90dd5a0 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv32.mir
@@ -107,10 +107,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY3]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY3]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[COPY]], [[COPY2]]
; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv32.mir
index 0c5830f5f1cd81..1c92dcf4b401ee 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv32.mir
@@ -107,10 +107,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY1]](s32), [[COPY3]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY1]](s32), [[COPY3]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[COPY]], [[COPY2]]
; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
diff --git a/llvm/test/CodeGen/X86/isel-select-cmov.ll b/llvm/test/CodeGen/X86/isel-select-cmov.ll
index 39a20bf6637bb8..fbd9bd073155e8 100644
--- a/llvm/test/CodeGen/X86/isel-select-cmov.ll
+++ b/llvm/test/CodeGen/X86/isel-select-cmov.ll
@@ -741,18 +741,18 @@ define i64 @select_cmp_cmov_i64(i64 %a, i64 %b) nounwind {
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; GISEL-X86-NEXT: cmpl %eax, %esi
+; GISEL-X86-NEXT: setb %bl
; GISEL-X86-NEXT: xorl %ecx, %ecx
; GISEL-X86-NEXT: cmpl %edx, %ebp
-; GISEL-X86-NEXT: setb %bl
-; GISEL-X86-NEXT: sete %cl
-; GISEL-X86-NEXT: cmpl %eax, %esi
; GISEL-X86-NEXT: setb %bh
+; GISEL-X86-NEXT: sete %cl
; GISEL-X86-NEXT: testl %ecx, %ecx
; GISEL-X86-NEXT: je LBB6_2
; GISEL-X86-NEXT: ## %bb.1:
-; GISEL-X86-NEXT: movb %bh, %bl
+; GISEL-X86-NEXT: movb %bl, %bh
; GISEL-X86-NEXT: LBB6_2:
-; GISEL-X86-NEXT: movzbl %bl, %edi
+; GISEL-X86-NEXT: movzbl %bh, %edi
; GISEL-X86-NEXT: andl $1, %edi
; GISEL-X86-NEXT: je LBB6_4
; GISEL-X86-NEXT: ## %bb.3:
@@ -779,16 +779,16 @@ define i64 @select_cmp_cmov_i64(i64 %a, i64 %b) nounwind {
; GISEL-X86-CMOV-NEXT: movl {{[0-9]+}}(%esp), %edx
; GISEL-X86-CMOV-NEXT: movl {{[0-9]+}}(%esp), %esi
; GISEL-X86-CMOV-NEXT: movl {{[0-9]+}}(%esp), %edi
-; GISEL-X86-CMOV-NEXT: xorl %ebx, %ebx
; GISEL-X86-CMOV-NEXT: xorl %ecx, %ecx
+; GISEL-X86-CMOV-NEXT: cmpl %esi, %ebp
+; GISEL-X86-CMOV-NEXT: setb %cl
+; GISEL-X86-CMOV-NEXT: xorl %ebx, %ebx
+; GISEL-X86-CMOV-NEXT: xorl %eax, %eax
; GISEL-X86-CMOV-NEXT: cmpl %edi, %edx
; GISEL-X86-CMOV-NEXT: setb %bl
-; GISEL-X86-CMOV-NEXT: sete %cl
-; GISEL-X86-CMOV-NEXT: xorl %eax, %eax
-; GISEL-X86-CMOV-NEXT: cmpl %esi, %ebp
-; GISEL-X86-CMOV-NEXT: setb %al
-; GISEL-X86-CMOV-NEXT: testl %ecx, %ecx
-; GISEL-X86-CMOV-NEXT: cmovnew %ax, %bx
+; GISEL-X86-CMOV-NEXT: sete %al
+; GISEL-X86-CMOV-NEXT: testl %eax, %eax
+; GISEL-X86-CMOV-NEXT: cmovnew %cx, %bx
; GISEL-X86-CMOV-NEXT: andl $1, %ebx
; GISEL-X86-CMOV-NEXT: cmovel %esi, %ebp
; GISEL-X86-CMOV-NEXT: cmovel %edi, %edx
>From 70ee6a4abf0b2092edb5d081985b76e1bfdd6dd1 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 9 Dec 2024 23:11:29 -0800
Subject: [PATCH 2/2] fixup! clang-format
---
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 21 +++++++++----------
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index a6997b7a27d450..dc659aea225d06 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -1785,12 +1785,11 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
}
if (!CmpIn) {
- MIRBuilder.buildICmp(PartPred, CmpOut,
- LHSPartRegs[I], RHSPartRegs[I]);
+ MIRBuilder.buildICmp(PartPred, CmpOut, LHSPartRegs[I],
+ RHSPartRegs[I]);
} else {
- auto Cmp =
- MIRBuilder.buildICmp(PartPred, ResTy,
- LHSPartRegs[I], RHSPartRegs[I]);
+ auto Cmp = MIRBuilder.buildICmp(PartPred, ResTy, LHSPartRegs[I],
+ RHSPartRegs[I]);
auto CmpEq = MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy,
LHSPartRegs[I], RHSPartRegs[I]);
MIRBuilder.buildSelect(CmpOut, CmpEq, CmpIn, Cmp);
@@ -1812,14 +1811,14 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
}
if (!CmpIn) {
- MIRBuilder.buildICmp(PartPred, CmpOut,
- LHSLeftoverRegs[I], RHSLeftoverRegs[I]);
+ MIRBuilder.buildICmp(PartPred, CmpOut, LHSLeftoverRegs[I],
+ RHSLeftoverRegs[I]);
} else {
- auto Cmp =
- MIRBuilder.buildICmp(PartPred, ResTy,
+ auto Cmp = MIRBuilder.buildICmp(PartPred, ResTy, LHSLeftoverRegs[I],
+ RHSLeftoverRegs[I]);
+ auto CmpEq =
+ MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy,
LHSLeftoverRegs[I], RHSLeftoverRegs[I]);
- auto CmpEq = MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy,
- LHSLeftoverRegs[I], RHSLeftoverRegs[I]);
MIRBuilder.buildSelect(CmpOut, CmpEq, CmpIn, Cmp);
}
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