[llvm] And sub combine (PR #119316)

[via llvm-commits]

https://github.com/fengfeng09 created https://github.com/llvm/llvm-project/pull/119316

None

>From 312c90d09d568ce87982d5867556c901bd8838a0 Mon Sep 17 00:00:00 2001
From: "feng.feng" <feng.feng at iluvatar.com>
Date: Tue, 10 Dec 2024 10:38:43 +0800
Subject: [PATCH 1/2] [InstCombine][NFC] Precommit testcase for and-sub
 combine.

---
 .../InstCombine/X86/and-sub-combine.ll           | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 llvm/test/Transforms/InstCombine/X86/and-sub-combine.ll

diff --git a/llvm/test/Transforms/InstCombine/X86/and-sub-combine.ll b/llvm/test/Transforms/InstCombine/X86/and-sub-combine.ll
new file mode 100644
index 00000000000000..5bf21629b13202
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/X86/and-sub-combine.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes=instcombine -mtriple=x86_64-unknown-unknown -S | FileCheck %s
+
+define i8 @and_sub(i8 %a) {
+; CHECK-LABEL: @and_sub(
+; CHECK-NEXT:    [[AND1:%.*]] = and i8 [[A:%.*]], 15
+; CHECK-NEXT:    [[AND2:%.*]] = and i8 [[A]], 3
+; CHECK-NEXT:    [[RET:%.*]] = sub nsw i8 [[AND1]], [[AND2]]
+; CHECK-NEXT:    ret i8 [[RET]]
+;
+  %and1 = and i8 %a, 15
+  %and2 = and i8 %a, 3
+
+  %ret = sub i8 %and1, %and2
+  ret i8 %ret
+}

>From cce5dac25218f2dd34393fb6758fe4db727e6055 Mon Sep 17 00:00:00 2001
From: "chenglin.bi" <chenglin.bi at iluvatar.com>
Date: Thu, 5 Dec 2024 10:12:08 +0800
Subject: [PATCH 2/2] [InstCombine] Add pattern 'if (C1 & C2) == C2 then (X &
 C1) - (X & C2) -> X & (C1 ^ C2)'

https://alive2.llvm.org/ce/z/BveKM5
---
 llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp   | 9 +++++++++
 llvm/test/Transforms/InstCombine/X86/and-sub-combine.ll | 4 +---
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
index ea7942ef978110..51831bba9c423b 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
@@ -2280,6 +2280,15 @@ Instruction *InstCombinerImpl::visitSub(BinaryOperator &I) {
   if (match(Op0, m_OneUse(m_Add(m_Value(X), m_AllOnes()))))
     return BinaryOperator::CreateAdd(Builder.CreateNot(Op1), X);
 
+  const APInt *C1, *C2;
+  // if (C1 & C2) == C2 then (X & C1) - (X & C2) -> X & (C1 ^ C2)
+  if (match(Op0, m_And(m_Value(X), m_APInt(C1))) &&
+      match(Op1, m_And(m_Specific(X), m_APInt(C2)))) {
+    if (C2->eq(*C1 & *C2))
+      return BinaryOperator::CreateAnd(
+          X, ConstantInt::get(I.getType(), *C1 ^ *C2));
+  }
+
   // Reassociate sub/add sequences to create more add instructions and
   // reduce dependency chains:
   // ((X - Y) + Z) - Op1 --> (X + Z) - (Y + Op1)
diff --git a/llvm/test/Transforms/InstCombine/X86/and-sub-combine.ll b/llvm/test/Transforms/InstCombine/X86/and-sub-combine.ll
index 5bf21629b13202..5120717bf1481a 100644
--- a/llvm/test/Transforms/InstCombine/X86/and-sub-combine.ll
+++ b/llvm/test/Transforms/InstCombine/X86/and-sub-combine.ll
@@ -3,9 +3,7 @@
 
 define i8 @and_sub(i8 %a) {
 ; CHECK-LABEL: @and_sub(
-; CHECK-NEXT:    [[AND1:%.*]] = and i8 [[A:%.*]], 15
-; CHECK-NEXT:    [[AND2:%.*]] = and i8 [[A]], 3
-; CHECK-NEXT:    [[RET:%.*]] = sub nsw i8 [[AND1]], [[AND2]]
+; CHECK-NEXT:    [[RET:%.*]] = and i8 [[A:%.*]], 12
 ; CHECK-NEXT:    ret i8 [[RET]]
 ;
   %and1 = and i8 %a, 15