[llvm] [RegAlloc] Scale the spill weight by the weight of register class (PR #113675)

[Matt Arsenault via llvm-commits]

arsenm wrote:

> Ah ok that makes sense to me at least for RISC-V, where a single LMUL 8 spill would be roughly the same as 8 * LMUL 1 spills. Does this hold for other targets though? E.g. could it be possible that spilling a register that uses two regunits costs the same as spilling another register that only uses one regunit?

It essentially does for AMDGPU. On most targets we end up splitting spills into 32-bit register (2-regunit, top one unaddressable) operations anyway. Newer targets can spill multiple registers at a time, but that's still N times more expensive 

https://github.com/llvm/llvm-project/pull/113675