[llvm] [RISCV] Prefer strided store for interleave store with one lane active (PR #119027)

[Philip Reames via llvm-commits]

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@@ -21906,6 +21906,7 @@ bool RISCVTargetLowering::lowerInterleavedStore(StoreInst *SI,
                                                 ShuffleVectorInst *SVI,
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preames wrote:

InterleavedAccessImpl::lowerInterleavedStore has an isSimple check at the very top before any of this code gets invoked.  

https://github.com/llvm/llvm-project/pull/119027