[llvm] [RISCV] Prefer strided store for interleave store with one lane active (PR #119027)

[via llvm-commits]

github-actions[bot] wrote:

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git-clang-format --diff 3c83054bec3326ccf338eeda56e67e8cd83a3b2a b077d05e7e225de5d4975ff116f29bc9b5dc346d --extensions cpp -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 743d68523b..5cd3a3f1c3 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -21933,10 +21933,10 @@ bool RISCVTargetLowering::lowerInterleavedStore(StoreInst *SI,
     Value *Mask = Builder.getAllOnesMask(DataVTy->getElementCount());
     Value *VL = Builder.getInt32(VTy->getNumElements());
 
-    CallInst *CI =
-        Builder.CreateIntrinsic(Intrinsic::experimental_vp_strided_store,
-                                {Data->getType(), BasePtr->getType(), Stride->getType()},
-                                {Data, BasePtr, Stride, Mask, VL});
+    CallInst *CI = Builder.CreateIntrinsic(
+        Intrinsic::experimental_vp_strided_store,
+        {Data->getType(), BasePtr->getType(), Stride->getType()},
+        {Data, BasePtr, Stride, Mask, VL});
     CI->addParamAttr(
         1, Attribute::getWithAlignment(CI->getContext(), SI->getAlign()));
 

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https://github.com/llvm/llvm-project/pull/119027