[llvm] [AMDGPU][Scheduler] Refactor VGPR rematerialization during scheduling (PR #118722)

[Lucas Ramirez via llvm-commits]

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@@ -1671,6 +1667,20 @@ void PreRARematStage::sinkTriviallyRematInsts(
     ImpactedRegions[Remat.DefRegion] = true;
   }
 
+  // Clean up the IR; remove rematerialized instructions from state.
+  for (auto &[NewMI, OldMI] : InsertedMIToOldDef) {
+    // Remove rematerialized instruction from BBLiveInMap since we are sinking
+    // it from its MBB.
+    DAG.BBLiveInMap.erase(OldMI);
+
+    // Remove the rematerialized instruction and update live intervals.
+    Register Reg = NewMI->getOperand(0).getReg();
+    DAG.LIS->RemoveMachineInstrFromMaps(*OldMI);
+    OldMI->eraseFromParent();
+    DAG.LIS->removeInterval(Reg);
+    DAG.LIS->createAndComputeVirtRegInterval(Reg);
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lucas-rami wrote:

Should be possible, working on this (might take me a minute since I am not so familiar with `LiveInterval` and related classes yet).

https://github.com/llvm/llvm-project/pull/118722