[llvm] [AMDGPU][Scheduler] Refactor VGPR rematerialization during scheduling (PR #118722)

[Lucas Ramirez via llvm-commits]

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@@ -1716,6 +1712,11 @@ bool PreRARematStage::isTriviallyReMaterializable(const MachineInstr &MI) {
   if (!DAG.TII->isTriviallyReMaterializable(MI))
     return false;
 
+  // Even though TargetInstrInfo::isReallyTriviallyReMaterializable already
+  // ensures that the instruction has no virtual register uses,
+  // SIInstrInfo::isReallyTriviallyReMaterializable may consider an instruction
+  // rematerializable and return before calling its parent's method, so we need
+  // to double-check here.
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lucas-rami wrote:

It is a bit confusing to me as well. Our `SIInstrInfo` override considers that rematerializing VOP{1,2,3} instructions with virtual register uses is trivial, which I don't really agree with. Removing the override in favor of its parent's method breaks many unit tests however, so if that's ok I will leave this as is for now and investigate this further in the future.

https://github.com/llvm/llvm-project/pull/118722