[llvm] IR: Allow vector type in atomic load and store (PR #117625)

[James Y Knight via llvm-commits]

jyknight wrote:

> Verifier checks can be disabled with -disable-verify, which already permits the lowering of atomic load/store with vector type in multiple targets

Currently, IR having load/store atomic with a vector type is invalid. If you disable the verifier and provide invalid IR to LLVM, what happens next may be arbitrary -- nobody should be depending on that.

So, I would strongly suggest that the first change be to _unconditionally_ cast the vector to integers -- both in the base class TargetLoweringBase::shouldCastAtomicLoadInIR/shouldCastAtomicStoreInIR and in all the overrides (looks like 3 of those: NVPTX, AMDGPU, SystemZ).

Then, you can make separate follow-up changes for each target to opt out of the cast when possible.


https://github.com/llvm/llvm-project/pull/117625