[llvm] [RISCV] Intrinsic Support for XCVsimd (PR #118557)

[Craig Topper via llvm-commits]

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@@ -415,6 +419,24 @@ bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
   return true;
 }
 
+bool RISCVExpandPseudo::expandVendorXcvsimdShuffle(MachineBasicBlock &MBB,
+                                                   MachineBasicBlock::iterator
+                                                   MBBI) {
+  DebugLoc DL = MBBI->getDebugLoc();
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topperc wrote:

Why are we doing this here instead of in isel?

https://github.com/llvm/llvm-project/pull/118557