[llvm] [RISCV] Intrinsic Support for XCVsimd (PR #118557)

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git-clang-format --diff 092a819e94da3fc0cac6982e99861546237fcb04 8fa72399a1cacb24b977c1ad0ac184bf34c7f17c --extensions cpp -- llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
index 08cabc7c47..06b2a05bd8 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -419,9 +419,8 @@ bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
   return true;
 }
 
-bool RISCVExpandPseudo::expandVendorXcvsimdShuffle(MachineBasicBlock &MBB,
-                                                   MachineBasicBlock::iterator
-                                                   MBBI) {
+bool RISCVExpandPseudo::expandVendorXcvsimdShuffle(
+    MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
   DebugLoc DL = MBBI->getDebugLoc();
   Register DstReg = MBBI->getOperand(0).getReg();
   Register SrcReg = MBBI->getOperand(1).getReg();

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https://github.com/llvm/llvm-project/pull/118557