[llvm] b8805c8 - [RISCV] Clang-format a few lines to remove diff in a nearby patch
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 3 10:42:26 PST 2024
Author: Philip Reames
Date: 2024-12-03T10:42:17-08:00
New Revision: b8805c88ce09fe8cc7e469162cbef05722559566
URL: https://github.com/llvm/llvm-project/commit/b8805c88ce09fe8cc7e469162cbef05722559566
DIFF: https://github.com/llvm/llvm-project/commit/b8805c88ce09fe8cc7e469162cbef05722559566.diff
LOG: [RISCV] Clang-format a few lines to remove diff in a nearby patch
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index b2e96b63a80953..1e185956bd30e4 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4440,10 +4440,10 @@ static SDValue lowerScalarInsert(SDValue Scalar, SDValue VL, MVT VT,
// a zero extend and the simm5 check in isel would fail.
// FIXME: Should we ignore the upper bits in isel instead?
unsigned ExtOpc =
- isa<ConstantSDNode>(Scalar) ? ISD::SIGN_EXTEND : ISD::ANY_EXTEND;
+ isa<ConstantSDNode>(Scalar) ? ISD::SIGN_EXTEND : ISD::ANY_EXTEND;
Scalar = DAG.getNode(ExtOpc, DL, XLenVT, Scalar);
- return DAG.getNode(RISCVISD::VMV_S_X_VL, DL, VT,
- DAG.getUNDEF(VT), Scalar, VL);
+ return DAG.getNode(RISCVISD::VMV_S_X_VL, DL, VT, DAG.getUNDEF(VT), Scalar,
+ VL);
}
// Is this a shuffle extracts either the even or odd elements of a vector?
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