[llvm] 4dd5ac9 - [RISCV] Improve coverage for spread(N) shuffles

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2024-12-03T10:42:17-08:00
New Revision: 4dd5ac906f9efdba3034b70acdda406348dc6f53

URL: https://github.com/llvm/llvm-project/commit/4dd5ac906f9efdba3034b70acdda406348dc6f53
DIFF: https://github.com/llvm/llvm-project/commit/4dd5ac906f9efdba3034b70acdda406348dc6f53.diff

LOG: [RISCV] Improve coverage for spread(N) shuffles

I'd already included a few cases for spread(N) in the decompress(N) variants,
but rename for clarity and add a couple more edge cases.

i.e. spread(N, 0) produces a, undef, b, undef, ...

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
index 5b01eae1ba3c05..21417fe8deefb7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
@@ -810,8 +810,8 @@ define <8 x i32> @shuffle_compress_singlesrc_gaps_e32(<8 x i32> %v) {
   ret <8 x i32> %out
 }
 
-define <8 x i32> @shuffle_decompress2_singlesrc_e32(<8 x i32> %v) {
-; CHECK-LABEL: shuffle_decompress2_singlesrc_e32:
+define <8 x i32> @shuffle_spread2_singlesrc_e32(<8 x i32> %v) {
+; CHECK-LABEL: shuffle_spread2_singlesrc_e32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
 ; CHECK-NEXT:    vwaddu.vv v10, v8, v8
@@ -823,18 +823,46 @@ define <8 x i32> @shuffle_decompress2_singlesrc_e32(<8 x i32> %v) {
   ret <8 x i32> %out
 }
 
-define <8 x i32> @shuffle_decompress3_singlesrc_e32(<8 x i32> %v) {
-; RV32-LABEL: shuffle_decompress3_singlesrc_e32:
+define <8 x i32> @shuffle_spread2_singlesrc_e32_index1(<8 x i32> %v) {
+; CHECK-LABEL: shuffle_spread2_singlesrc_e32_index1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT:    vwaddu.vv v10, v8, v8
+; CHECK-NEXT:    li a0, -1
+; CHECK-NEXT:    vwmaccu.vx v10, a0, v8
+; CHECK-NEXT:    vmv2r.v v8, v10
+; CHECK-NEXT:    ret
+  %out = shufflevector <8 x i32> %v, <8 x i32> poison, <8 x i32> <i32 undef, i32 0, i32 undef, i32 1, i32 undef, i32 2, i32 undef, i32 3>
+  ret <8 x i32> %out
+}
+
+define <8 x i32> @shuffle_spread2_singlesrc_e32_index2(<8 x i32> %v) {
+; CHECK-LABEL: shuffle_spread2_singlesrc_e32_index2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vid.v v10
+; CHECK-NEXT:    vsrl.vi v10, v10, 1
+; CHECK-NEXT:    vadd.vi v12, v10, -1
+; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT:    vrgatherei16.vv v10, v8, v12
+; CHECK-NEXT:    vmv.v.v v8, v10
+; CHECK-NEXT:    ret
+  %out = shufflevector <8 x i32> %v, <8 x i32> poison, <8 x i32> <i32 undef, i32 undef, i32 0, i32 undef, i32 1, i32 undef, i32 2, i32 undef>
+  ret <8 x i32> %out
+}
+
+define <8 x i32> @shuffle_spread3_singlesrc_e32(<8 x i32> %v) {
+; RV32-LABEL: shuffle_spread3_singlesrc_e32:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, %hi(.LCPI55_0)
-; RV32-NEXT:    addi a0, a0, %lo(.LCPI55_0)
+; RV32-NEXT:    lui a0, %hi(.LCPI57_0)
+; RV32-NEXT:    addi a0, a0, %lo(.LCPI57_0)
 ; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
 ; RV32-NEXT:    vle16.v v12, (a0)
 ; RV32-NEXT:    vrgatherei16.vv v10, v8, v12
 ; RV32-NEXT:    vmv.v.v v8, v10
 ; RV32-NEXT:    ret
 ;
-; RV64-LABEL: shuffle_decompress3_singlesrc_e32:
+; RV64-LABEL: shuffle_spread3_singlesrc_e32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    lui a0, 32769
 ; RV64-NEXT:    slli a0, a0, 21
@@ -849,8 +877,8 @@ define <8 x i32> @shuffle_decompress3_singlesrc_e32(<8 x i32> %v) {
 }
 
 ; TODO: This should be a single vslideup.vi
-define <8 x i32> @shuffle_decompress4_singlesrc_e32(<8 x i32> %v) {
-; CHECK-LABEL: shuffle_decompress4_singlesrc_e32:
+define <8 x i32> @shuffle_spread4_singlesrc_e32(<8 x i32> %v) {
+; CHECK-LABEL: shuffle_spread4_singlesrc_e32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
 ; CHECK-NEXT:    vid.v v10
@@ -864,8 +892,8 @@ define <8 x i32> @shuffle_decompress4_singlesrc_e32(<8 x i32> %v) {
 }
 
 ; TODO: This should be either a single vslideup.vi or two widening interleaves.
-define <8 x i8> @shuffle_decompress4_singlesrc_e8(<8 x i8> %v) {
-; CHECK-LABEL: shuffle_decompress4_singlesrc_e8:
+define <8 x i8> @shuffle_spread4_singlesrc_e8(<8 x i8> %v) {
+; CHECK-LABEL: shuffle_spread4_singlesrc_e8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
 ; CHECK-NEXT:    vid.v v9
@@ -877,11 +905,25 @@ define <8 x i8> @shuffle_decompress4_singlesrc_e8(<8 x i8> %v) {
   ret <8 x i8> %out
 }
 
+define <32 x i8> @shuffle_spread8_singlesrc_e8(<32 x i8> %v) {
+; CHECK-LABEL: shuffle_spread8_singlesrc_e8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 32
+; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
+; CHECK-NEXT:    vid.v v10
+; CHECK-NEXT:    vsrl.vi v12, v10, 3
+; CHECK-NEXT:    vrgather.vv v10, v8, v12
+; CHECK-NEXT:    vmv.v.v v8, v10
+; CHECK-NEXT:    ret
+  %out = shufflevector <32 x i8> %v, <32 x i8> poison, <32 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  ret <32 x i8> %out
+}
+
 define <8 x i32> @shuffle_decompress_singlesrc_e32(<8 x i32> %v) {
 ; CHECK-LABEL: shuffle_decompress_singlesrc_e32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lui a0, %hi(.LCPI58_0)
-; CHECK-NEXT:    addi a0, a0, %lo(.LCPI58_0)
+; CHECK-NEXT:    lui a0, %hi(.LCPI61_0)
+; CHECK-NEXT:    addi a0, a0, %lo(.LCPI61_0)
 ; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
 ; CHECK-NEXT:    vle16.v v12, (a0)
 ; CHECK-NEXT:    vrgatherei16.vv v10, v8, v12