[llvm] [AMDGPU][True16][CodeGen] FLAT_load using D16 pseudo instruction (PR #114500)

Matt Arsenault via llvm-commits llvm-commits at lists.llvm.org
Tue Dec 3 06:55:56 PST 2024


================
@@ -132,6 +133,35 @@ void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
     OutMI.addOperand(Dest);
     OutMI.addOperand(Src);
     return;
+  } else if (const auto *Info = AMDGPU::getT16D16Helper(Opcode)) {
+    int VDataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata);
+    int VDstOrVDataIdx = VDataIdx != -1 ? VDataIdx : 0;
+    MachineOperand MIVDstOrVData = MI->getOperand(VDstOrVDataIdx);
+    bool IsHi = AMDGPU::isHi16Reg(MIVDstOrVData.getReg(), TRI);
+    Opcode = IsHi ? Info->HiOp : Info->LoOp;
+    MIVDstOrVData.clearParent(); // Avoid use list error in setReg call
+    MIVDstOrVData.setReg(TRI.get32BitRegister(MIVDstOrVData.getReg()));
+
+    int MCOpcode = TII->pseudoToMCOpcode(Opcode);
+    assert(MCOpcode != -1 &&
+           "Pseudo instruction doesn't have a target-specific version");
+    OutMI.setOpcode(MCOpcode);
+    for (int I = 0, E = MI->getNumExplicitOperands(); I < E; I++) {
+      const MachineOperand &MO = MI->getOperand(I);
+      MCOperand MCOp;
+      if (I == VDstOrVDataIdx)
+        lowerOperand(MIVDstOrVData, MCOp);
+      else
+        lowerOperand(MO, MCOp);
+      OutMI.addOperand(MCOp);
+    }
+
----------------
arsenm wrote:

I don't understand why this needs so much custom fixing up 

https://github.com/llvm/llvm-project/pull/114500


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