[llvm] [AMDGPU][True16][CodeGen] FLAT_load using D16 pseudo instruction (PR #114500)

[Matt Arsenault via llvm-commits]

================
@@ -132,6 +133,35 @@ void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
     OutMI.addOperand(Dest);
     OutMI.addOperand(Src);
     return;
+  } else if (const auto *Info = AMDGPU::getT16D16Helper(Opcode)) {
+    int VDataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata);
+    int VDstOrVDataIdx = VDataIdx != -1 ? VDataIdx : 0;
+    MachineOperand MIVDstOrVData = MI->getOperand(VDstOrVDataIdx);
+    bool IsHi = AMDGPU::isHi16Reg(MIVDstOrVData.getReg(), TRI);
+    Opcode = IsHi ? Info->HiOp : Info->LoOp;
+    MIVDstOrVData.clearParent(); // Avoid use list error in setReg call
+    MIVDstOrVData.setReg(TRI.get32BitRegister(MIVDstOrVData.getReg()));
----------------
arsenm wrote:

Don't use MachineOperands by value. You shouldn't be fixing up MIR when you're just trying to pass this into an MCInst, just set the regitser directly 

https://github.com/llvm/llvm-project/pull/114500