[llvm] [RISCV] Clear vill for whole vector register moves in vsetvli insertion (PR #118283)

[Luke Lau via llvm-commits]

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@@ -1208,6 +1232,17 @@ static VSETVLIInfo adjustIncoming(VSETVLIInfo PrevInfo, VSETVLIInfo NewInfo,
 // legal for MI, but may not be the state requested by MI.
 void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
                                         const MachineInstr &MI) const {
+  if (isVectorCopy(ST->getRegisterInfo(), MI) &&
+      (Info.isUnknown() || !Info.isValid() || Info.hasSEWLMULRatioOnly())) {
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lukel97 wrote:

Agreed, I originally didn't include it but it looks like we always need to clear hasSEWLMULRationOnly after transferBefore if something might end up inserting a vsetvli. Otherwise we trigger an assertion in emitVSETVLIs

https://github.com/llvm/llvm-project/pull/118283