[llvm] [RISCV] Clear vill for whole vector register moves in vsetvli insertion (PR #118283)

[Luke Lau via llvm-commits]

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@@ -195,6 +195,14 @@ static bool hasUndefinedPassthru(const MachineInstr &MI) {
   return UseMO.getReg() == RISCV::NoRegister || UseMO.isUndef();
 }
 
+/// Return true if \p MI is a copy that will be lowered to one or more vmvNr.vs.
+static bool isVectorCopy(const TargetRegisterInfo *TRI,
+                         const MachineInstr &MI) {
+  return MI.isCopy() && MI.getOperand(0).getReg().isPhysical() &&
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lukel97 wrote:

>From what I understood they also take part in vector register allocation? The tuple register classes have the `IsVRegClass` TSFlag set, which is what `isRVVRegClass` checks for. I think the copy in `vlsegff-rv64.ll` is a segmented tuple, and it seems to be picked up in this PR. cc @4vtomat 

https://github.com/llvm/llvm-project/pull/118283