[llvm] [DAGISel][ARM] Fix vector truncate combine for big-endian (PR #118101)

[Oliver Stannard via llvm-commits]

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@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=armebv7-unknown-none-eabihf -mattr=+neon < %s | FileCheck %s
+
+define i32 @test(i64 %arg1) "target-features"="+neon" {
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ostannard wrote:

Done

https://github.com/llvm/llvm-project/pull/118101