[llvm] [DAGISel][ARM] Fix vector truncate combine for big-endian (PR #118101)

[Oliver Stannard via llvm-commits]

https://github.com/ostannard updated https://github.com/llvm/llvm-project/pull/118101

>From 7fb3d04e4c1cccb03f428e01d516466ef95a9e58 Mon Sep 17 00:00:00 2001
From: Oliver Stannard <oliver.stannard at arm.com>
Date: Fri, 29 Nov 2024 14:43:30 +0000
Subject: [PATCH 1/3] Add test showing bug

---
 llvm/test/CodeGen/ARM/big-endian-vector-trunc.ll | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 llvm/test/CodeGen/ARM/big-endian-vector-trunc.ll

diff --git a/llvm/test/CodeGen/ARM/big-endian-vector-trunc.ll b/llvm/test/CodeGen/ARM/big-endian-vector-trunc.ll
new file mode 100644
index 00000000000000..5de8bf477e53e1
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/big-endian-vector-trunc.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=armebv7-unknown-none-eabihf -mattr=+neon < %s | FileCheck %s
+
+define i32 @test(i64 %arg1) "target-features"="+neon" {
+; CHECK-LABEL: test:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    mov r0, #0
+; CHECK-NEXT:    bx lr
+entry:
+  %insert_zero = insertelement <8 x i64> poison, i64 %arg1, i64 0
+  %splat_zero = shufflevector <8 x i64> %insert_zero, <8 x i64> poison, <8 x i32> zeroinitializer
+  %cmp_vec = icmp ule <8 x i64> <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>, %splat_zero
+  %first_cmp = extractelement <8 x i1> %cmp_vec, i32 0
+  %ext = zext i1 %first_cmp to i32
+  ret i32 %ext
+}

>From 700a90545d68d7f4e40ccee5de67b2f7c7c85d9e Mon Sep 17 00:00:00 2001
From: Oliver Stannard <oliver.stannard at arm.com>
Date: Fri, 29 Nov 2024 14:45:33 +0000
Subject: [PATCH 2/3] [DAGISel][ARM] Fix vector truncate combine for big-endian

This DAG combine was incorrect for big-endian targets, because it
assumes that when a bitcast changes the lane width, the
least-significant bits of the wider lanes are in the lower-numbered
lanes of the smaller type, which is only true for little-endian.
---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp   |  5 ++++-
 .../test/CodeGen/ARM/big-endian-vector-trunc.ll | 17 ++++++++++++++++-
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 521829675ae7c3..90aa3009fb5ef0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -15495,12 +15495,15 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
       unsigned BuildVecNumElts =  BuildVect.getNumOperands();
       unsigned TruncVecNumElts = VT.getVectorNumElements();
       unsigned TruncEltOffset = BuildVecNumElts / TruncVecNumElts;
+      unsigned FirstElt =
+          DAG.getDataLayout().isBigEndian() ? (TruncEltOffset - 1) : 0;
 
       assert((BuildVecNumElts % TruncVecNumElts) == 0 &&
              "Invalid number of elements");
 
       SmallVector<SDValue, 8> Opnds;
-      for (unsigned i = 0, e = BuildVecNumElts; i != e; i += TruncEltOffset)
+      for (unsigned i = FirstElt, e = BuildVecNumElts; i < e;
+           i += TruncEltOffset)
         Opnds.push_back(BuildVect.getOperand(i));
 
       return DAG.getBuildVector(VT, DL, Opnds);
diff --git a/llvm/test/CodeGen/ARM/big-endian-vector-trunc.ll b/llvm/test/CodeGen/ARM/big-endian-vector-trunc.ll
index 5de8bf477e53e1..cdc09754d2654c 100644
--- a/llvm/test/CodeGen/ARM/big-endian-vector-trunc.ll
+++ b/llvm/test/CodeGen/ARM/big-endian-vector-trunc.ll
@@ -4,8 +4,23 @@
 define i32 @test(i64 %arg1) "target-features"="+neon" {
 ; CHECK-LABEL: test:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    mov r0, #0
+; CHECK-NEXT:    subs r1, r1, #1
+; CHECK-NEXT:    mov r2, #0
+; CHECK-NEXT:    sbcs r0, r0, #0
+; CHECK-NEXT:    vldr s0, .LCPI0_0
+; CHECK-NEXT:    movwhs r2, #1
+; CHECK-NEXT:    cmp r2, #0
+; CHECK-NEXT:    mvnne r2, #0
+; CHECK-NEXT:    vmov s1, r2
+; CHECK-NEXT:    vmovn.i32 d16, q0
+; CHECK-NEXT:    vmovn.i16 d16, q8
+; CHECK-NEXT:    vmov.u8 r0, d16[0]
+; CHECK-NEXT:    and r0, r0, #1
 ; CHECK-NEXT:    bx lr
+; CHECK-NEXT:    .p2align 2
+; CHECK-NEXT:  @ %bb.1:
+; CHECK-NEXT:  .LCPI0_0:
+; CHECK-NEXT:    .long 0xffffffff @ float NaN
 entry:
   %insert_zero = insertelement <8 x i64> poison, i64 %arg1, i64 0
   %splat_zero = shufflevector <8 x i64> %insert_zero, <8 x i64> poison, <8 x i32> zeroinitializer

>From 804db3d27fbdbb45241c6e8179ecc97ab62d6cf1 Mon Sep 17 00:00:00 2001
From: Oliver Stannard <oliver.stannard at arm.com>
Date: Fri, 29 Nov 2024 15:42:39 +0000
Subject: [PATCH 3/3] Remove unneeded target-features attribute

---
 llvm/test/CodeGen/ARM/big-endian-vector-trunc.ll | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/test/CodeGen/ARM/big-endian-vector-trunc.ll b/llvm/test/CodeGen/ARM/big-endian-vector-trunc.ll
index cdc09754d2654c..15a4f2e37ca469 100644
--- a/llvm/test/CodeGen/ARM/big-endian-vector-trunc.ll
+++ b/llvm/test/CodeGen/ARM/big-endian-vector-trunc.ll
@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -mtriple=armebv7-unknown-none-eabihf -mattr=+neon < %s | FileCheck %s
 
-define i32 @test(i64 %arg1) "target-features"="+neon" {
+define i32 @test(i64 %arg1) {
 ; CHECK-LABEL: test:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    subs r1, r1, #1