[llvm] 22fdc57 - [Hexagon] Avoid implicit truncation in getConstant()
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 22 06:08:45 PST 2024
Author: Nikita Popov
Date: 2024-11-22T15:07:31+01:00
New Revision: 22fdc57140283d053207ea5763dc03ec7770a8ff
URL: https://github.com/llvm/llvm-project/commit/22fdc57140283d053207ea5763dc03ec7770a8ff
DIFF: https://github.com/llvm/llvm-project/commit/22fdc57140283d053207ea5763dc03ec7770a8ff.diff
LOG: [Hexagon] Avoid implicit truncation in getConstant()
Use getSignedConstant() or change variable type as appropriate.
This will avoid assertion failures when implicit truncation is
disabled.
Added:
Modified:
llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
llvm/lib/Target/Hexagon/HexagonIntrinsics.td
llvm/lib/Target/Hexagon/HexagonPatterns.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
index b6ed035607d960..2c20db16b055ff 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -135,7 +135,7 @@ void HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl) {
llvm_unreachable("Unexpected memory type in indexed load");
}
- SDValue IncV = CurDAG->getTargetConstant(Inc, dl, MVT::i32);
+ SDValue IncV = CurDAG->getSignedTargetConstant(Inc, dl, MVT::i32);
MachineMemOperand *MemOp = LD->getMemOperand();
auto getExt64 = [this,ExtType] (MachineSDNode *N, const SDLoc &dl)
@@ -213,7 +213,8 @@ MachineSDNode *HexagonDAGToDAGISel::LoadInstrForLoadIntrinsic(SDNode *IntN) {
EVT RTys[] = { ValTy, MVT::i32, MVT::Other };
// Operands: { Base, Increment, Modifier, Chain }
auto Inc = cast<ConstantSDNode>(IntN->getOperand(5));
- SDValue I = CurDAG->getTargetConstant(Inc->getSExtValue(), dl, MVT::i32);
+ SDValue I =
+ CurDAG->getSignedTargetConstant(Inc->getSExtValue(), dl, MVT::i32);
MachineSDNode *Res = CurDAG->getMachineNode(FLC->second, dl, RTys,
{ IntN->getOperand(2), I, IntN->getOperand(4),
IntN->getOperand(0) });
@@ -531,7 +532,7 @@ void HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl) {
dl, MVT::i32, Value);
}
- SDValue IncV = CurDAG->getTargetConstant(Inc, dl, MVT::i32);
+ SDValue IncV = CurDAG->getSignedTargetConstant(Inc, dl, MVT::i32);
MachineMemOperand *MemOp = ST->getMemOperand();
// Next address Chain
@@ -889,7 +890,7 @@ void HexagonDAGToDAGISel::SelectV2Q(SDNode *N) {
MVT OpTy = N->getOperand(0).getValueType().getSimpleVT(); (void)OpTy;
assert(HST->getVectorLength() * 8 == OpTy.getSizeInBits());
- SDValue C = CurDAG->getTargetConstant(-1, dl, MVT::i32);
+ SDValue C = CurDAG->getSignedTargetConstant(-1, dl, MVT::i32);
SDNode *R = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32, C);
SDNode *T = CurDAG->getMachineNode(Hexagon::V6_vandvrt, dl, ResTy,
N->getOperand(0), SDValue(R,0));
@@ -902,7 +903,7 @@ void HexagonDAGToDAGISel::SelectQ2V(SDNode *N) {
// The result of V2Q should be a single vector.
assert(HST->getVectorLength() * 8 == ResTy.getSizeInBits());
- SDValue C = CurDAG->getTargetConstant(-1, dl, MVT::i32);
+ SDValue C = CurDAG->getSignedTargetConstant(-1, dl, MVT::i32);
SDNode *R = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32, C);
SDNode *T = CurDAG->getMachineNode(Hexagon::V6_vandqrt, dl, ResTy,
N->getOperand(0), SDValue(R,0));
@@ -1491,7 +1492,7 @@ inline bool HexagonDAGToDAGISel::SelectAnyInt(SDValue &N, SDValue &R) {
EVT T = N.getValueType();
if (!T.isInteger() || T.getSizeInBits() != 32 || !isa<ConstantSDNode>(N))
return false;
- int32_t V = cast<const ConstantSDNode>(N)->getZExtValue();
+ uint32_t V = cast<const ConstantSDNode>(N)->getZExtValue();
R = CurDAG->getTargetConstant(V, SDLoc(N), N.getValueType());
return true;
}
@@ -1502,7 +1503,7 @@ bool HexagonDAGToDAGISel::SelectAnyImmediate(SDValue &N, SDValue &R,
case ISD::Constant: {
if (N.getValueType() != MVT::i32)
return false;
- int32_t V = cast<const ConstantSDNode>(N)->getZExtValue();
+ uint32_t V = cast<const ConstantSDNode>(N)->getZExtValue();
if (!isAligned(Alignment, V))
return false;
R = CurDAG->getTargetConstant(V, SDLoc(N), N.getValueType());
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 08a9c95ee7359f..2c8d141aa21080 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -2557,10 +2557,10 @@ HexagonTargetLowering::buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl,
if (ElemTy == MVT::i8) {
// First try generating a constant.
if (AllConst) {
- int32_t V = (Consts[0]->getZExtValue() & 0xFF) |
- (Consts[1]->getZExtValue() & 0xFF) << 8 |
- (Consts[2]->getZExtValue() & 0xFF) << 16 |
- Consts[3]->getZExtValue() << 24;
+ uint32_t V = (Consts[0]->getZExtValue() & 0xFF) |
+ (Consts[1]->getZExtValue() & 0xFF) << 8 |
+ (Consts[2]->getZExtValue() & 0xFF) << 16 |
+ Consts[3]->getZExtValue() << 24;
return DAG.getBitcast(MVT::v4i8, DAG.getConstant(V, dl, MVT::i32));
}
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index dd951d7eb8b54a..ab0f41343ce211 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -1203,8 +1203,9 @@ HexagonTargetLowering::insertHvxElementReg(SDValue VecV, SDValue IdxV,
SDValue ByteIdxV) {
MVT VecTy = ty(VecV);
unsigned HwLen = Subtarget.getVectorLength();
- SDValue MaskV = DAG.getNode(ISD::AND, dl, MVT::i32,
- {ByteIdxV, DAG.getConstant(-4, dl, MVT::i32)});
+ SDValue MaskV =
+ DAG.getNode(ISD::AND, dl, MVT::i32,
+ {ByteIdxV, DAG.getSignedConstant(-4, dl, MVT::i32)});
SDValue RotV = DAG.getNode(HexagonISD::VROR, dl, VecTy, {VecV, MaskV});
SDValue InsV = DAG.getNode(HexagonISD::VINSERTW0, dl, VecTy, {RotV, ValV});
SDValue SubV = DAG.getNode(ISD::SUB, dl, MVT::i32,
@@ -1882,7 +1883,7 @@ HexagonTargetLowering::LowerHvxCttz(SDValue Op, SelectionDAG &DAG) const {
SDValue VecW = DAG.getNode(ISD::SPLAT_VECTOR, dl, ResTy,
DAG.getConstant(ElemWidth, dl, MVT::i32));
SDValue VecN1 = DAG.getNode(ISD::SPLAT_VECTOR, dl, ResTy,
- DAG.getConstant(-1, dl, MVT::i32));
+ DAG.getAllOnesConstant(dl, MVT::i32));
// Do not use DAG.getNOT, because that would create BUILD_VECTOR with
// a BITCAST. Here we can skip the BITCAST (so we don't have to handle
@@ -2264,7 +2265,7 @@ SDValue HexagonTargetLowering::LowerHvxFpExtend(SDValue Op,
SDValue ShuffVec =
getInstr(Hexagon::V6_vshuffvdd, dl, VecTy,
- {HiVec, LoVec, DAG.getConstant(-4, dl, MVT::i32)}, DAG);
+ {HiVec, LoVec, DAG.getSignedConstant(-4, dl, MVT::i32)}, DAG);
return ShuffVec;
}
@@ -2416,7 +2417,7 @@ HexagonTargetLowering::emitHvxAddWithOverflow(SDValue A, SDValue B,
// i.e. (~A xor B) & ((A+B) xor B), then check the sign bit
SDValue Add = DAG.getNode(ISD::ADD, dl, ResTy, {A, B});
SDValue NotA =
- DAG.getNode(ISD::XOR, dl, ResTy, {A, DAG.getConstant(-1, dl, ResTy)});
+ DAG.getNode(ISD::XOR, dl, ResTy, {A, DAG.getAllOnesConstant(dl, ResTy)});
SDValue Xor0 = DAG.getNode(ISD::XOR, dl, ResTy, {NotA, B});
SDValue Xor1 = DAG.getNode(ISD::XOR, dl, ResTy, {Add, B});
SDValue And = DAG.getNode(ISD::AND, dl, ResTy, {Xor0, Xor1});
@@ -3620,7 +3621,7 @@ HexagonTargetLowering::PerformHvxDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
case HexagonISD::Q2V:
if (Ops[0].getOpcode() == HexagonISD::QTRUE)
return DAG.getNode(ISD::SPLAT_VECTOR, dl, ty(Op),
- DAG.getConstant(-1, dl, MVT::i32));
+ DAG.getAllOnesConstant(dl, MVT::i32));
if (Ops[0].getOpcode() == HexagonISD::QFALSE)
return getZero(dl, ty(Op), DAG);
break;
diff --git a/llvm/lib/Target/Hexagon/HexagonIntrinsics.td b/llvm/lib/Target/Hexagon/HexagonIntrinsics.td
index 6f20c823df8551..25b81d8cd21ff0 100644
--- a/llvm/lib/Target/Hexagon/HexagonIntrinsics.td
+++ b/llvm/lib/Target/Hexagon/HexagonIntrinsics.td
@@ -148,12 +148,12 @@ class S2op_tableidx_pat <Intrinsic IntID, InstHexagon OutputInst,
def SDEC2 : SDNodeXForm<imm, [{
int32_t V = N->getSExtValue();
- return CurDAG->getTargetConstant(V-2, SDLoc(N), MVT::i32);
+ return CurDAG->getSignedTargetConstant(V-2, SDLoc(N), MVT::i32);
}]>;
def SDEC3 : SDNodeXForm<imm, [{
int32_t V = N->getSExtValue();
- return CurDAG->getTargetConstant(V-3, SDLoc(N), MVT::i32);
+ return CurDAG->getSignedTargetConstant(V-3, SDLoc(N), MVT::i32);
}]>;
// Table Index : Extract and insert bits.
diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td
index baa552fcd220d8..52fa73f3798c37 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatterns.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td
@@ -171,7 +171,7 @@ class IsUGT<int Width, int Arg>: PatLeaf<(i32 imm),
def SDEC1: SDNodeXForm<imm, [{
int32_t V = N->getSExtValue();
- return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32);
+ return CurDAG->getSignedTargetConstant(V-1, SDLoc(N), MVT::i32);
}]>;
def UDEC1: SDNodeXForm<imm, [{
@@ -388,12 +388,12 @@ def Uitofp: pf1<uint_to_fp>;
//
def Imm64Lo: SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(int32_t (N->getSExtValue()),
- SDLoc(N), MVT::i32);
+ return CurDAG->getSignedTargetConstant(int32_t(N->getSExtValue()),
+ SDLoc(N), MVT::i32);
}]>;
def Imm64Hi: SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(int32_t (N->getSExtValue()>>32),
- SDLoc(N), MVT::i32);
+ return CurDAG->getSignedTargetConstant(int32_t(N->getSExtValue()>>32),
+ SDLoc(N), MVT::i32);
}]>;
@@ -406,7 +406,7 @@ def HexagonCONST32: SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
def HexagonCONST32_GP: SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
def TruncI64ToI32: SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
+ return CurDAG->getSignedTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
}]>;
def: Pat<(s32_0ImmPred:$s16), (A2_tfrsi imm:$s16)>;
@@ -2597,14 +2597,14 @@ def IMM_BYTE : SDNodeXForm<imm, [{
// -1 can be represented as 255, etc.
// assigning to a byte restores our desired signed value.
int8_t imm = N->getSExtValue();
- return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32);
+ return CurDAG->getSignedTargetConstant(imm, SDLoc(N), MVT::i32);
}]>;
def IMM_HALF : SDNodeXForm<imm, [{
// -1 can be represented as 65535, etc.
// assigning to a short restores our desired signed value.
int16_t imm = N->getSExtValue();
- return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32);
+ return CurDAG->getSignedTargetConstant(imm, SDLoc(N), MVT::i32);
}]>;
def IMM_WORD : SDNodeXForm<imm, [{
@@ -2613,7 +2613,7 @@ def IMM_WORD : SDNodeXForm<imm, [{
// might convert -1 to a large +ve number.
// assigning to a word restores our desired signed value.
int32_t imm = N->getSExtValue();
- return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32);
+ return CurDAG->getSignedTargetConstant(imm, SDLoc(N), MVT::i32);
}]>;
def ToImmByte : OutPatFrag<(ops node:$R), (IMM_BYTE $R)>;
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