[llvm] [RISC-V] Support fixed vector type for inline asm (#117098) (PR #117100)

[Zhijin Zeng via llvm-commits]

zengdage wrote:

> > > This kind of seems like a frontend bug. Why did clang pass it as a fixed vecor? Removing `__attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen * lmul)))` works as expected.
> > 
> > 
> > Do you mean that all the inline asm parameters should be scalable vector types rather than fixed vector types? So I need to fix why clang pass fixed vector types to inline asm?
> 
> Yes. Without `__attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen * lmul)))` the inline asm parameters are scalable vectors. I don't think the attribute was supposed to change that.

I read the clang CodeGen code, and find that fixed-length vector types will be represented as scalable vector types in function args and return value by `coerceVLSVector,` but not do this when emit inline asm. I don't know whether it's a issue or fixed-length vector types don't need to be represented in inline asm. 
But from my Superficial knowledge, I think why do this in function args and return value is because need to comply with calling convention, but inline asm isn't a real function call and don't need to comply with it. The inline asm has no prototype, it should use what legal parameter types you give it. The attribute actually changes the parameter type which is legal for llvm ir, so need to pass it as fixed vector type. What do you think?

https://github.com/llvm/llvm-project/pull/117100