[llvm] [AArch64] Generate zeroing forms of certain SVE2.2 instructions (2/11) (PR #116828)

[via llvm-commits]

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@@ -4260,7 +4268,7 @@ let Predicates = [HasSVE2p2orSME2p2] in {
   // SVE2p2 floating-point convert single-to-bf (placing odd), zeroing predicate
   def BFCVTNT_ZPzZ      : sve_fp_fcvt2z<0b1010, "bfcvtnt", ZPR16, ZPR32>;
   // Placing corresponding
-  def BFCVT_ZPzZ_StoH   : sve_fp_z2op_p_zd<0b1001010, "bfcvt", ZPR32, ZPR16>;
+  defm BFCVT_ZPzZ_StoH  : sve_fp_z2op_p_zd_bfcvt<0b1001010, "bfcvt", int_aarch64_sve_fcvt_bf16f32_v2>;
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SpencerAbson wrote:

No strong opinion, but we could move the bit-string into the multiclass here seeing as it is only used for `bfcvt`.

https://github.com/llvm/llvm-project/pull/116828