[llvm] [AArch64] Generate zeroing forms of certain SVE2.2 instructions (2/11) (PR #116828)

[via llvm-commits]

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@@ -3296,13 +3310,20 @@ multiclass sve_fp_z2op_p_zd_d_flogb<string asm> {
   def _D : sve_fp_z2op_p_zd<0b0011011, asm, ZPR64, ZPR64>;
 }
 
-multiclass sve_fp_z2op_p_zd_b_0<string asm> {
+multiclass sve_fp_z2op_p_zd_b_0<string asm, string op> {
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SpencerAbson wrote:

Worth renaming `op` to `int_op`?

IIUC, we currently match `SVE_1_Op_PassthruUndef_Pat` for the `AArch64fcvtr`/`AArch64fcvte` operands only - the codegen here will not be improved as it would be for the intrinsic, am I correct in understanding that this is out of the scope of this work?

https://github.com/llvm/llvm-project/pull/116828