[llvm] [RISCV] Fix the worst case for VSHA2MS in SiFive P400/P600 scheduling models (PR #116893)

[Min-Yih Hsu via llvm-commits]

mshockwave wrote:

We might also want to teach TableGen to warn or even throw an error on cases like this (i.e. duplicate WriteRes assignments)

https://github.com/llvm/llvm-project/pull/116893