[llvm] [AMDGPU][MC][True16] Support VOP2 instructions with true16 format (PR #115233)

[Brox Chen via llvm-commits]

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@@ -345,6 +345,25 @@ static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm,
                               (AMDGPU::OperandSemantics)OperandSemantics));
 }
 
+template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
+          unsigned OperandSemantics>
+static DecodeStatus
+decodeOperand_VSrcT16_Lo128_Deferred(MCInst &Inst, unsigned Imm,
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broxigarchen wrote:

I think it can be combined but I think it's better to seperate them. It's a naming convension in this file that the deferred decoder has the defered name on the function

https://github.com/llvm/llvm-project/pull/115233