[llvm] [AMDGPU][True16][MC] support more VOP3 inst in true16/fake16 format (PR #113603)

[Ivan Kosarev via llvm-commits]

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@@ -1891,47 +1891,47 @@ v_lshrrev_b16_e64_dpp v5.l, v1.l, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bo
 v_lshrrev_b16_e64_dpp v255.h, v255.l, v255.l row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 // GFX11: [0xff,0x40,0x39,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
 
-v_mad_i16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+v_mad_i16_e64_dpp v5.l, v1.l, v2.l, v3.l quad_perm:[3,2,1,0]
 // GFX11: [0x05,0x00,0x53,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
 
-v_mad_i16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
-// GFX11: [0x05,0x00,0x53,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+v_mad_i16_e64_dpp v5.h, v1.h, v2.h, v3.h quad_perm:[0,1,2,3]
+// GFX11: [0x05,0x78,0x53,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
 
-v_mad_i16_e64_dpp v5, v1, v2, v3 row_mirror
-// GFX11: [0x05,0x00,0x53,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+v_mad_i16_e64_dpp v5.l, v1.l, v2.l, v255.h row_mirror
+// GFX11: [0x05,0x20,0x53,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff]
 
-v_mad_i16_e64_dpp v5, v1, v2, v3 row_half_mirror
-// GFX11: [0x05,0x00,0x53,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
+v_mad_i16_e64_dpp v5.l, v1.l, v2.l, s3 row_half_mirror
+// GFX11: [0x05,0x00,0x53,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x41,0x01,0xff]
 
-v_mad_i16_e64_dpp v5, v1, v2, v255 row_shl:1
-// GFX11: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
+v_mad_i16_e64_dpp v5.l, v1.l, v2.l, s105 row_shl:1
+// GFX11: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
 
-v_mad_i16_e64_dpp v5, v1, v2, s105 row_shl:15
-// GFX11: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
+v_mad_i16_e64_dpp v5.l, v1.l, v2.l, ttmp15 row_shl:15
+// GFX11: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xee,0x01,0x01,0x0f,0x01,0xff]
 
-v_mad_i16_e64_dpp v5, v1, v2, vcc_hi row_shr:1
+v_mad_i16_e64_dpp v5.l, v1.l, v2.l, vcc_hi row_shr:1
 // GFX11: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
 
-v_mad_i16_e64_dpp v5, v1, v2, vcc_lo row_shr:15
+v_mad_i16_e64_dpp v5.l, v1.l, v2.l, vcc_lo row_shr:15
 // GFX11: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
 
-v_mad_i16_e64_dpp v5, v1, v2, ttmp15 row_ror:1
-// GFX11: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff]
+v_mad_i16_e64_dpp v5.l, v1.l, v2.l, m0 row_ror:1
+// GFX11: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xf6,0x01,0x01,0x21,0x01,0xff]
 
-v_mad_i16_e64_dpp v5, v1, v2, exec_hi row_ror:15
-// GFX11: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
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kosarev wrote:

Looks like this removes all `row_ror:15` cases?

https://github.com/llvm/llvm-project/pull/113603