[llvm] [RISCV][MachineVerifier] Use RegUnit for register liveness checking (PR #115980)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,21 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=none %s -o - | FileCheck %s
+
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arsenm wrote:

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https://github.com/llvm/llvm-project/pull/115980