[llvm] [RISCV][MachineVerifier] Use RegUnit for register liveness checking (PR #115980)

[Piyou Chen via llvm-commits]

================
@@ -3035,6 +3035,16 @@ void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
 
             if (llvm::is_contained(TRI->subregs(MOP.getReg()), Reg))
               Bad = false;
+
+            if (any_of(TRI->subregs(MOP.getReg()),
----------------
BeMg wrote:

To avoid this problem, I modified to check only when `MOP.getReg()` does not equal `Reg`.

```
if (MOP.getReg() != Reg && all_of(TRI->regunits(Reg), [&](const MCRegUnit RegUnit) {
      return llvm::is_contained(TRI->regunits(MOP.getReg()),
                                RegUnit);
    }))
```

https://github.com/llvm/llvm-project/pull/115980