[llvm] AMDGPU: Update pattern matching from "x&(-1>>(32-y))" to "bfe x, 0, y" (PR #116115)

[Jay Foad via llvm-commits]

jayfoad wrote:

> The description in the RDNA3 ISA says D0.u = ((S0.u >> S1.u[4 : 0].u) & 32'U((1 << S2.u[4 : 0].u) - 1))

This says that it only looks at bits 4:0 of S2, so 32 would be treated the same as 0.

https://github.com/llvm/llvm-project/pull/116115