[llvm] AMDGPU: Update pattern matching from "x&(-1>>(32-y))" to "bfe x, 0, y" (PR #116115)

[Diana Picus via llvm-commits]

rovka wrote:

Hi, I like your patch but I have a couple of questions:
* Where does it say that `v_bfe_u32 x, 0, 32` is 0? The description in [the RDNA3 ISA](https://www.amd.com/content/dam/amd/en/documents/radeon-tech-docs/instruction-set-architectures/rdna3-shader-instruction-set-architecture-feb-2023_0.pdf) says `D0.u = ((S0.u >> S1.u[4 : 0].u) & 32'U((1 << S2.u[4 : 0].u) - 1))`, which is unfortunately not very specific about edge cases. I would interpret it as large values cause the 1 to be shifted out, then when we subtract 1 we get 0xFFF...F, so when we do & with it we essentially get x. If the hardware actually returns 0, we should probably talk to folks to make that clear in the ISA.
* While you're at it, what do `v_bfe_i32` and `s_bfe_*` do and do we have proper tests for them?

https://github.com/llvm/llvm-project/pull/116115