[llvm] [AMDGPU] Mark AGPR tuple implicit in the first instr of AGPR spills. (PR #115285)

[Christudasan Devadasan via llvm-commits]

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@@ -1808,6 +1808,8 @@ void SIRegisterInfo::buildSpillLoadStore(
                            .addReg(SubReg, getKillRegState(IsKill));
         if (NeedSuperRegDef)
           AccRead.addReg(ValueReg, RegState::ImplicitDefine);
+        if (NeedSuperRegImpOperand && (IsFirstSubReg || IsLastSubReg))
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cdevadas wrote:

I would get this patch done first as we are not aggravating the complexity related to spill handling further. By adding implicit operands to the first and last subreg insns, this patch aligns the partial spill case (partially in VGPR and the rest into memory) to other vector spill cases handled in this function. Pravin can continue work on a follow-up patch to align it similar to the COPY expansion.

https://github.com/llvm/llvm-project/pull/115285