[llvm] [AMDGPU] Mark AGPR tuple implicit in the first instr of AGPR spills. (PR #115285)

[Matt Arsenault via llvm-commits]

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@@ -1808,6 +1808,8 @@ void SIRegisterInfo::buildSpillLoadStore(
                            .addReg(SubReg, getKillRegState(IsKill));
         if (NeedSuperRegDef)
           AccRead.addReg(ValueReg, RegState::ImplicitDefine);
+        if (NeedSuperRegImpOperand && (IsFirstSubReg || IsLastSubReg))
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arsenm wrote:

We're just fighting an uphill battle against bad infrastructure. Needing these extra operands to represent liveness is terrible. 

I think we should migrate to having explicit operands carrying regmasks. Currently that will make MachineOperand bigger, but I think we can find space savings elsewhere. 

https://github.com/llvm/llvm-project/pull/115285