[llvm] [RISCV][MachineVerifier] Use RegUnit for register liveness checking (PR #115980)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,73 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=machineverifier %s -o - | FileCheck %s
+
+...
+---
+name:            func
+tracksRegLiveness: true
+tracksDebugUserValues: true
+body:             |
+  bb.0:
+    liveins: $v0, $v8, $v9, $v10, $v11
+
+    ; CHECK-LABEL: name: func
+    ; CHECK: liveins: $v0, $v8, $v9, $v10, $v11
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -16
+    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
+    ; CHECK-NEXT: $x10 = frame-setup PseudoReadVLENB
+    ; CHECK-NEXT: $x11 = frame-setup ADDI $x0, 10
+    ; CHECK-NEXT: $x10 = frame-setup MUL killed $x10, killed $x11
+    ; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x10
+    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x0a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22
+    ; CHECK-NEXT: dead renamable $x10 = PseudoVSETVLIX0 killed $x0, 193 /* e8, m2, ta, ma */, implicit-def $vl, implicit-def $vtype
+    ; CHECK-NEXT: renamable $v16m2 = PseudoVMV_V_I_M2 undef renamable $v16m2, 0, -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: renamable $v12m2 = PseudoVMERGE_VIM_M2 undef renamable $v12m2, renamable $v16m2, 1, $v0, -1, 3 /* e8 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: $v0 = VMV1R_V killed $v8, implicit $v8
+    ; CHECK-NEXT: renamable $v24m2 = PseudoVMERGE_VIM_M2 undef renamable $v24m2, renamable $v16m2, 1, $v0, -1, 3 /* e8 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: $v18m2 = VMV2R_V $v12m2, implicit $v12_v13_v14_v15_v16
+    ; CHECK-NEXT: $v20m2 = VMV2R_V $v14m2, implicit $v12_v13_v14_v15_v16
+    ; CHECK-NEXT: $v22 = VMV1R_V $v16, implicit $v12_v13_v14_v15_v16
+    ; CHECK-NEXT: $v0 = VMV1R_V $v9, implicit $v9
+    ; CHECK-NEXT: $v19 = VMV1R_V $v24, implicit $v24
+    ; CHECK-NEXT: renamable $v14m2 = PseudoVMERGE_VIM_M2 undef renamable $v14m2, renamable $v16m2, 1, $v0, -1, 3 /* e8 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: $x12 = ADDI $x0, 1
+    ; CHECK-NEXT: early-clobber renamable $v0 = PseudoVSLIDEUP_VX_M1 killed renamable $v0, killed renamable $v9, killed renamable $x12, $noreg, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: dead renamable $x10 = PseudoVSETVLIX0 killed $x0, 193 /* e8, m2, ta, ma */, implicit-def $vl, implicit-def $vtype
+    ; CHECK-NEXT: early-clobber renamable $v8 = PseudoVMSNE_VI_M2 killed renamable $v10m2, 0, -1, 3 /* e8 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: $x10 = frame-destroy PseudoReadVLENB
+    ; CHECK-NEXT: $x11 = frame-destroy ADDI $x0, 10
+    ; CHECK-NEXT: $x10 = frame-destroy MUL killed $x10, killed $x11
+    ; CHECK-NEXT: $x2 = frame-destroy ADD $x2, killed $x10
+    ; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 16
+    ; CHECK-NEXT: PseudoRET implicit $v0, implicit $v8
+    $x2 = frame-setup ADDI $x2, -16
+    frame-setup CFI_INSTRUCTION def_cfa_offset 16
+    $x10 = frame-setup PseudoReadVLENB
+    $x11 = frame-setup ADDI $x0, 10
+    $x10 = frame-setup MUL killed $x10, killed $x11
+    $x2 = frame-setup SUB $x2, killed $x10
+    frame-setup CFI_INSTRUCTION escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x0a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22
+    dead renamable $x10 = PseudoVSETVLIX0 killed $x0, 193 /* e8, m2, ta, ma */, implicit-def $vl, implicit-def $vtype
+    renamable $v16m2 = PseudoVMV_V_I_M2 undef renamable $v16m2, 0, -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
+    renamable $v12m2 = PseudoVMERGE_VIM_M2 undef renamable $v12m2, renamable $v16m2, 1, $v0, -1, 3 /* e8 */, implicit $vl, implicit $vtype
+    $v0 = VMV1R_V killed $v8, implicit $v8
+    renamable $v24m2 = PseudoVMERGE_VIM_M2 undef renamable $v24m2, renamable $v16m2, 1, $v0, -1, 3 /* e8 */, implicit $vl, implicit $vtype
+    $v18m2 = VMV2R_V $v12m2, implicit $v12_v13_v14_v15_v16
+    $v20m2 = VMV2R_V $v14m2, implicit $v12_v13_v14_v15_v16
+    $v22 = VMV1R_V $v16, implicit $v12_v13_v14_v15_v16
+    $v0 = VMV1R_V $v9, implicit $v9
+    $v19 = VMV1R_V $v24, implicit $v24
+    renamable $v14m2 = PseudoVMERGE_VIM_M2 undef renamable $v14m2, renamable $v16m2, 1, $v0, -1, 3 /* e8 */, implicit $vl, implicit $vtype
+    $x12 = ADDI $x0, 1
+    early-clobber renamable $v0 = PseudoVSLIDEUP_VX_M1 killed renamable $v0, killed renamable $v9, killed renamable $x12, $noreg, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype
+    dead renamable $x10 = PseudoVSETVLIX0 killed $x0, 193 /* e8, m2, ta, ma */, implicit-def $vl, implicit-def $vtype
+    early-clobber renamable $v8 = PseudoVMSNE_VI_M2 killed renamable $v10m2, 0, -1, 3 /* e8 */, implicit $vl, implicit $vtype
+    $x10 = frame-destroy PseudoReadVLENB
+    $x11 = frame-destroy ADDI $x0, 10
+    $x10 = frame-destroy MUL killed $x10, killed $x11
+    $x2 = frame-destroy ADD $x2, killed $x10
+    $x2 = frame-destroy ADDI $x2, 16
+    PseudoRET implicit $v0, implicit $v8
----------------
arsenm wrote:

This should reducible to a few instructions 

https://github.com/llvm/llvm-project/pull/115980