[llvm] [RISCV][MRI] Account for fixed registers when determining callee saved regs (PR #115756)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 11 11:35:42 PST 2024
https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/115756
>From 55641bb6831c13ecf60414a805ba51fee34a0793 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Mon, 11 Nov 2024 07:32:42 -0800
Subject: [PATCH 1/3] [RISCV][RegAlloc] Pre-commit test case
---
.../CodeGen/RISCV/fixed-global-regalloc.ll | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/fixed-global-regalloc.ll
diff --git a/llvm/test/CodeGen/RISCV/fixed-global-regalloc.ll b/llvm/test/CodeGen/RISCV/fixed-global-regalloc.ll
new file mode 100644
index 00000000000000..f814f578bf98fc
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/fixed-global-regalloc.ll
@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc %s -mtriple=riscv64 -mattr=+reserve-x24 | FileCheck %s
+
+define i32 @main() {
+; CHECK-LABEL: main:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: sd s8, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT: .cfi_offset s8, -8
+; CHECK-NEXT: li s8, 123
+; CHECK-NEXT: li a0, 0
+; CHECK-NEXT: ld s8, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT: .cfi_restore s8
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.write_register.i64(metadata !0, i64 123)
+ ret i32 0
+}
+
+declare void @llvm.write_register.i64(metadata, i64) #1
+
+!llvm.named.register.x24 = !{!0}
+
+!0 = !{!"x24"}
+
>From 3c661fe58a2fc3524dde5742529808f39c989e8f Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Mon, 11 Nov 2024 10:31:51 -0800
Subject: [PATCH 2/3] [MRI][RISCV] Account for fixed registers when determining
callee saved regs
---
llvm/include/llvm/CodeGen/TargetSubtargetInfo.h | 2 ++
llvm/lib/CodeGen/MachineRegisterInfo.cpp | 8 +++++++-
llvm/lib/Target/M68k/M68kRegisterInfo.cpp | 2 +-
llvm/lib/Target/M68k/M68kSubtarget.h | 2 +-
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 3 +--
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVSubtarget.h | 2 +-
llvm/test/CodeGen/RISCV/fixed-global-regalloc.ll | 8 --------
8 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
index bfaa6450779ae0..6b14d1476568f9 100644
--- a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
@@ -339,6 +339,8 @@ class TargetSubtargetInfo : public MCSubtargetInfo {
// Conservatively assume such instructions exist by default.
return true;
}
+
+ virtual bool isRegisterReservedByUser(Register R) const { return false; }
};
} // end namespace llvm
diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
index fcedb302d228c4..6f636a161f5000 100644
--- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
@@ -635,7 +635,13 @@ const MCPhysReg *MachineRegisterInfo::getCalleeSavedRegs() const {
if (IsUpdatedCSRsInitialized)
return UpdatedCSRs.data();
- return getTargetRegisterInfo()->getCalleeSavedRegs(MF);
+ const MCPhysReg *Regs = getTargetRegisterInfo()->getCalleeSavedRegs(MF);
+
+ for (unsigned I = 0; Regs[I]; ++I)
+ if (MF->getSubtarget().isRegisterReservedByUser(Regs[I]))
+ MF->getRegInfo().disableCalleeSavedRegister(Regs[I]);
+
+ return Regs;
}
void MachineRegisterInfo::setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs) {
diff --git a/llvm/lib/Target/M68k/M68kRegisterInfo.cpp b/llvm/lib/Target/M68k/M68kRegisterInfo.cpp
index 62fb72ba4fd5e4..0f6b4761f2cb8a 100644
--- a/llvm/lib/Target/M68k/M68kRegisterInfo.cpp
+++ b/llvm/lib/Target/M68k/M68kRegisterInfo.cpp
@@ -136,7 +136,7 @@ BitVector M68kRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
// Registers reserved by users
for (size_t Reg = 0, Total = getNumRegs(); Reg != Total; ++Reg) {
- if (MF.getSubtarget<M68kSubtarget>().isRegisterReservedByUser(Reg))
+ if (MF.getSubtarget().isRegisterReservedByUser(Reg))
setBitVector(Reg);
}
diff --git a/llvm/lib/Target/M68k/M68kSubtarget.h b/llvm/lib/Target/M68k/M68kSubtarget.h
index 3fbec2f72fb861..c08a9786fb27ba 100644
--- a/llvm/lib/Target/M68k/M68kSubtarget.h
+++ b/llvm/lib/Target/M68k/M68kSubtarget.h
@@ -107,7 +107,7 @@ class M68kSubtarget : public M68kGenSubtargetInfo {
bool isPositionIndependent() const;
- bool isRegisterReservedByUser(Register R) const {
+ bool isRegisterReservedByUser(Register R) const override {
assert(R < M68k::NUM_TARGET_REGS && "Register out of range");
return UserReservedRegister[R];
}
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 831b0b30d47fcc..c8c495327c383f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -19884,8 +19884,7 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
// reserved, if so report an error. Do the same for the return address if this
// is not a tailcall.
validateCCReservedRegs(RegsToPass, MF);
- if (!IsTailCall &&
- MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(RISCV::X1))
+ if (!IsTailCall && MF.getSubtarget().isRegisterReservedByUser(RISCV::X1))
MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{
MF.getFunction(),
"Return address register required, but has been reserved."});
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 26195ef721db39..4b3b1d5154e9f6 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -163,7 +163,7 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF,
MCRegister PhysReg) const {
- return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg);
+ return !MF.getSubtarget().isRegisterReservedByUser(PhysReg);
}
const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index f59a3737ae76f9..99edf22eb0791f 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -218,7 +218,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
TargetABI == RISCVABI::ABI_ILP32 ||
TargetABI == RISCVABI::ABI_ILP32E;
}
- bool isRegisterReservedByUser(Register i) const {
+ bool isRegisterReservedByUser(Register i) const override {
assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
return UserReservedRegister[i];
}
diff --git a/llvm/test/CodeGen/RISCV/fixed-global-regalloc.ll b/llvm/test/CodeGen/RISCV/fixed-global-regalloc.ll
index f814f578bf98fc..f1993ae142ae8f 100644
--- a/llvm/test/CodeGen/RISCV/fixed-global-regalloc.ll
+++ b/llvm/test/CodeGen/RISCV/fixed-global-regalloc.ll
@@ -4,16 +4,8 @@
define i32 @main() {
; CHECK-LABEL: main:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: sd s8, 8(sp) # 8-byte Folded Spill
-; CHECK-NEXT: .cfi_offset s8, -8
; CHECK-NEXT: li s8, 123
; CHECK-NEXT: li a0, 0
-; CHECK-NEXT: ld s8, 8(sp) # 8-byte Folded Reload
-; CHECK-NEXT: .cfi_restore s8
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret
entry:
tail call void @llvm.write_register.i64(metadata !0, i64 123)
>From 958aeb31c243d0c295936b46017a52342747c5df Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Mon, 11 Nov 2024 11:34:27 -0800
Subject: [PATCH 3/3] fixup! fix test checks RUN string
---
.../RISCV/{fixed-global-regalloc.ll => fixed-csr.ll} | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
rename llvm/test/CodeGen/RISCV/{fixed-global-regalloc.ll => fixed-csr.ll} (78%)
diff --git a/llvm/test/CodeGen/RISCV/fixed-global-regalloc.ll b/llvm/test/CodeGen/RISCV/fixed-csr.ll
similarity index 78%
rename from llvm/test/CodeGen/RISCV/fixed-global-regalloc.ll
rename to llvm/test/CodeGen/RISCV/fixed-csr.ll
index f1993ae142ae8f..284d244717c196 100644
--- a/llvm/test/CodeGen/RISCV/fixed-global-regalloc.ll
+++ b/llvm/test/CodeGen/RISCV/fixed-csr.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc %s -mtriple=riscv64 -mattr=+reserve-x24 | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x24 < %s | FileCheck %s
-define i32 @main() {
-; CHECK-LABEL: main:
+define i32 @foo() {
+; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li s8, 123
; CHECK-NEXT: li a0, 0
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