[llvm] [llvm-exegesis][X86] Groups ports 2, 3, and 11 for Golden Cove (PR #115645)

[Aiden Grossman via llvm-commits]

boomanaiden154 wrote:

> Intel Architecture day also use port 2 3 10.

There doesn't seem to be any explicit groupings in the Architecture Day Slides? Those sides also list port 10 as being ALU/LEA and port 11 as being LOAD/AGU. That matches the association in the optimization manual.

This also matches the behavior of the current scheduling models AlderLake/SapphireRapids scheduling models.

https://github.com/llvm/llvm-project/pull/115645