[llvm] [AMDGPU] Mark AGPR tuple implicit in the first instr of AGPR spills. (PR #115285)

[Jeffrey Byrnes via llvm-commits]

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@@ -1808,6 +1808,8 @@ void SIRegisterInfo::buildSpillLoadStore(
                            .addReg(SubReg, getKillRegState(IsKill));
         if (NeedSuperRegDef)
           AccRead.addReg(ValueReg, RegState::ImplicitDefine);
+        if (NeedSuperRegImpOperand && (IsFirstSubReg || IsLastSubReg))
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jrbyrnes wrote:

> marking implicit to only first and last spill instrs will free up some unneeded dependencies for the post-ra scheduler

Yes by reducing the implicit / implicit-def noise, we will reduce the dependencies in post-ra scheduling, which will allow the scheduler more flexibility for better scheduling.

Not to mention that these operands confuse the calls to MI.modifies/defines/reads Register -- by increasing the amount of implicit / implicit-def operands I assume we are just increasing our exposure to this. 

> copyPhysReg and the spill expansions should have similar behavior

I'm not sure either why I didn't make these changes to the copy lowering, but I agree it should behave the same. 

I think we are probably going to continue running into problems for these implicit / implicit-def operands until we can use liveness queries when doing the lowering. That said, I'm fine with adding back the implicit operands if that works best with the calls to modifies/defines/reads Register

https://github.com/llvm/llvm-project/pull/115285