[llvm] [VPlan] Impl VPlan-based pattern match for ExtendedRed and MulAccRed (NFCI) (PR #113903)

[Elvis Wang via llvm-commits]

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@@ -2653,6 +2657,260 @@ class VPReductionEVLRecipe : public VPReductionRecipe {
   }
 };
 
+/// A recipe to represent inloop extended reduction operations, performing a
+/// reduction on a vector operand into a scalar value, and adding the result to
+/// a chain. This recipe is high level abstract which will generate
+/// VPReductionRecipe and VPWidenCastRecipe before execution. The Operands are
+/// {ChainOp, VecOp, [Condition]}.
+class VPExtendedReductionRecipe : public VPSingleDefRecipe {
+  /// The recurrence decriptor for the reduction in question.
+  const RecurrenceDescriptor &RdxDesc;
+  bool IsOrdered;
+  /// Whether the reduction is conditional.
+  bool IsConditional = false;
+  /// Type after extend.
+  Type *ResultTy;
+  /// Opcode for the extend instruction.
+  Instruction::CastOps ExtOp;
+  CastInst *ExtInstr;
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ElvisWang123 wrote:

Yes we can remove all underlying instruction but that will generate some duplicate vector instructions when there are multiple MulAcc or ExtendedReduction in the same vector loop and share same extend instructions.
We can find some test changed in [234e81e](https://github.com/llvm/llvm-project/pull/113903/commits/234e81ee87184b277b4f4b17ac222737fbf114eb)

https://github.com/llvm/llvm-project/pull/113903