[llvm] Zext sext undef in sdag (PR #115451)

[via llvm-commits]

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@@ -77,5 +77,15 @@ entry:
   %alphaXbetaY = add i64 %alphaX, %tmp115
   %transformed = add i64 %alphaXbetaY, 9040145182981852475
   store i64 %transformed, ptr %d, align 8
+  %tmp200 = zext i16 undef to i32
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fengfeng09 wrote:

two 16 bit undef composed a zero？

https://github.com/llvm/llvm-project/pull/115451