[llvm] 1d6d073 - [AArch64] Remove FeatureUseScalarIncVL
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sun Nov 10 06:52:00 PST 2024
Author: David Green
Date: 2024-11-10T14:51:55Z
New Revision: 1d6d073fbbaebbde6891501fe20f02a0ea345131
URL: https://github.com/llvm/llvm-project/commit/1d6d073fbbaebbde6891501fe20f02a0ea345131
DIFF: https://github.com/llvm/llvm-project/commit/1d6d073fbbaebbde6891501fe20f02a0ea345131.diff
LOG: [AArch64] Remove FeatureUseScalarIncVL
FeatureUseScalarIncVL is a tuning feature, used to control whether addvl or
add+cnt is used. It was previously added as a dependency for FeatureSVE2, an
architecture feature but this can be seen as a layering violation. The main
disadvantage is that -use-scalar-inc-vl cannot be used without disabling sve2
and all dependant features.
This patch now replaces that with an option that if unset defaults to hasSVE ||
hasSME, but is otherwise overriden by the option. The hope is that no cpus will
rely on the tuning feature (or we can readdit if needed.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64Features.td
llvm/lib/Target/AArch64/AArch64Subtarget.cpp
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll
llvm/test/CodeGen/AArch64/sve-vl-arith.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index 6d8554cf1884c1..a2349079889175 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -358,12 +358,9 @@ def FeatureTHE : ExtensionWithMArch<"the", "THE", "FEAT_THE",
// Armv9.0 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureUseScalarIncVL : SubtargetFeature<"use-scalar-inc-vl",
- "UseScalarIncVL", "true", "Prefer inc/dec over add+cnt">;
-
def FeatureSVE2 : ExtensionWithMArch<"sve2", "SVE2", "FEAT_SVE2",
"Enable Scalable Vector Extension 2 (SVE2) instructions",
- [FeatureSVE, FeatureUseScalarIncVL]>;
+ [FeatureSVE]>;
def FeatureSVE2AES : ExtensionWithMArch<"sve2-aes", "SVE2AES",
"FEAT_SVE_AES, FEAT_SVE_PMULL128",
@@ -403,7 +400,7 @@ def FeatureRME : Extension<"rme", "RME", "FEAT_RME",
"Enable Realm Management Extension">;
def FeatureSME : ExtensionWithMArch<"sme", "SME", "FEAT_SME",
- "Enable Scalable Matrix Extension (SME)", [FeatureBF16, FeatureUseScalarIncVL]>;
+ "Enable Scalable Matrix Extension (SME)", [FeatureBF16]>;
def FeatureSMEF64F64 : ExtensionWithMArch<"sme-f64f64", "SMEF64F64", "FEAT_SME_F64F64",
"Enable Scalable Matrix Extension (SME) F64F64 instructions", [FeatureSME]>;
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
index 736d57e6ae2fd9..bc11b2e06cf1c1 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -93,6 +93,10 @@ static cl::opt<bool>
cl::init(false), cl::Hidden,
cl::desc("Enable subreg liveness tracking"));
+static cl::opt<bool>
+ UseScalarIncVL("sve-use-scalar-inc-vl", cl::init(false), cl::Hidden,
+ cl::desc("Prefer add+cnt over addvl/inc/dec"));
+
unsigned AArch64Subtarget::getVectorInsertExtractBaseCost() const {
if (OverrideVectorInsertExtractBaseCost.getNumOccurrences() > 0)
return OverrideVectorInsertExtractBaseCost;
@@ -575,6 +579,14 @@ void AArch64Subtarget::mirFileLoaded(MachineFunction &MF) const {
bool AArch64Subtarget::useAA() const { return UseAA; }
+bool AArch64Subtarget::useScalarIncVL() const {
+ // If SVE2 or SME is present (we are not SVE-1 only) and UseScalarIncVL
+ // is not otherwise set, enable it by default.
+ if (UseScalarIncVL.getNumOccurrences())
+ return UseScalarIncVL;
+ return hasSVE2() || hasSME();
+}
+
// If return address signing is enabled, tail calls are emitted as follows:
//
// ```
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index f3dcce3f3994ba..7f5883289c6ddd 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -417,6 +417,10 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
return DefaultSVETFOpts;
}
+ /// Returns true to use the addvl/inc/dec instructions, as opposed to separate
+ /// add + cnt instructions.
+ bool useScalarIncVL() const;
+
const char* getChkStkName() const {
if (isWindowsArm64EC())
return "#__chkstk_arm64ec";
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll
index 5062a43da931f8..02d172fbc9dbfd 100644
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s -check-prefix=NO_SCALAR_INC
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -mattr=+use-scalar-inc-vl < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -sve-use-scalar-inc-vl=true < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
; INCB
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll
index 8f0a9eac87c27c..4e1ff4abd6ffdf 100644
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll
@@ -1,8 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -mattr=+use-scalar-inc-vl < %s | FileCheck %s -check-prefix=USE_SCALAR_INC
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -sve-use-scalar-inc-vl=true < %s | FileCheck %s -check-prefix=USE_SCALAR_INC
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s -check-prefix=USE_SCALAR_INC
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s -check-prefix=USE_SCALAR_INC
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 -sve-use-scalar-inc-vl=false < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -sve-use-scalar-inc-vl=false -force-streaming < %s | FileCheck %s
;
; CNTB
diff --git a/llvm/test/CodeGen/AArch64/sve-vl-arith.ll b/llvm/test/CodeGen/AArch64/sve-vl-arith.ll
index de2af590acd1e2..dad357c8a0c132 100644
--- a/llvm/test/CodeGen/AArch64/sve-vl-arith.ll
+++ b/llvm/test/CodeGen/AArch64/sve-vl-arith.ll
@@ -1,7 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -verify-machineinstrs < %s | FileCheck %s -check-prefix=NO_SCALAR_INC
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -mattr=+use-scalar-inc-vl -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -sve-use-scalar-inc-vl=true -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 -sve-use-scalar-inc-vl=false -verify-machineinstrs < %s | FileCheck %s -check-prefix=NO_SCALAR_INC
define <vscale x 8 x i16> @inch_vec(<vscale x 8 x i16> %a) {
; NO_SCALAR_INC-LABEL: inch_vec:
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