[llvm] [GlobalISel] Add G_STEP_VECTOR instruction (PR #115598)
Thorsten Schütt via llvm-commits
llvm-commits at lists.llvm.org
Sat Nov 9 23:32:28 PST 2024
https://github.com/tschuett updated https://github.com/llvm/llvm-project/pull/115598
>From 9b54f227f36a5a408b1c326be6e63498afb1a55f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= <schuett at gmail.com>
Date: Sat, 9 Nov 2024 10:52:19 +0100
Subject: [PATCH 1/7] [GlobalISel] Add G_STEP_VECTOR instruction
aka llvm.stepvector Intrinsic
---
llvm/docs/GlobalISel/GenericOpcode.rst | 16 ++++++++++
.../CodeGen/GlobalISel/GenericMachineInstrs.h | 10 +++++++
.../CodeGen/GlobalISel/MachineIRBuilder.h | 23 ++++++++++++++
llvm/include/llvm/Support/TargetOpcodes.def | 3 ++
llvm/include/llvm/Target/GenericOpcodes.td | 7 +++++
.../CodeGen/GlobalISel/MachineIRBuilder.cpp | 16 +++++++++-
llvm/lib/CodeGen/MachineVerifier.cpp | 30 +++++++++++++++++++
.../GlobalISel/legalizer-info-validation.mir | 3 ++
.../test/MachineVerifier/test_step-vector.mir | 29 ++++++++++++++++++
9 files changed, 136 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/MachineVerifier/test_step-vector.mir
diff --git a/llvm/docs/GlobalISel/GenericOpcode.rst b/llvm/docs/GlobalISel/GenericOpcode.rst
index 8920530dc3f1a1..b360d4ba35b80e 100644
--- a/llvm/docs/GlobalISel/GenericOpcode.rst
+++ b/llvm/docs/GlobalISel/GenericOpcode.rst
@@ -753,6 +753,22 @@ The type of the operand must be equal to or larger than the vector element
type. If the operand is larger than the vector element type, the scalar is
implicitly truncated to the vector element type.
+G_STEP_VECTOR
+^^^^^^^^^^^^^^^^
+
+Create a scalable vector where all lanes are linear sequences starting at 0
+with a given unsigned step.
+
+The type of the operand must be equal to the vector element type.
+
+.. code-block::
+
+ %0:_(<vscale x 2 x s64>) = G_STEP_VECTOR i64 4
+
+ %1:_(<vscale x s32>) = G_STEP_VECTOR i32 4
+
+ 0, 1*Step, 2*Step, 3*Step, 4*Step, ...
+
G_VECTOR_COMPRESS
^^^^^^^^^^^^^^^^^
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
index cd7ebcf54c9e1e..2c507633e1771d 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
@@ -906,6 +906,16 @@ class GVScale : public GenericMachineInstr {
};
};
+/// Represents a step vector.
+class GStepVector : public GenericMachineInstr {
+public:
+ APInt getStep() const { return getOperand(1).getCImm()->getValue(); }
+
+ static bool classof(const MachineInstr *MI) {
+ return MI->getOpcode() == TargetOpcode::G_STEP_VECTOR;
+ };
+};
+
/// Represents an integer subtraction.
class GSub : public GIntBinOp {
public:
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index a38dd34a17097a..37ea9c4b9a124f 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -1172,6 +1172,29 @@ class MachineIRBuilder {
MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src,
const SrcOp &Op, unsigned Index);
+ /// Build and insert \p Res = G_STEP_VECTOR \p Step
+ ///
+ /// G_STEP_VECTOR returns a scalable vector of linear sequence of step \p Step
+ /// into \p Res.
+ ///
+ /// \pre setBasicBlock or setMI must have been called.
+ /// \pre \p Res must be a generic virtual register with scalar type.
+ ///
+ /// \return a MachineInstrBuilder for the newly created instruction.
+ MachineInstrBuilder buildStepVector(const DstOp &Res,
+ const ConstantInt &Step);
+
+ /// Build and insert \p Res = G_STEP_VECTOR \p Step
+ ///
+ /// G_STEP_VECTOR returns a scalable vector of linear sequence of step \p Step
+ /// into \p Res.
+ ///
+ /// \pre setBasicBlock or setMI must have been called.
+ /// \pre \p Res must be a generic virtual register with scalar type.
+ ///
+ /// \return a MachineInstrBuilder for the newly created instruction.
+ MachineInstrBuilder buildStepVector(const DstOp &Res, const APInt &Step);
+
/// Build and insert \p Res = G_VSCALE \p MinElts
///
/// G_VSCALE puts the value of the runtime vscale multiplied by \p MinElts
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index 0c4c6ccd5c568e..17987935ed3cf4 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -776,6 +776,9 @@ HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR)
/// Generic splatvector.
HANDLE_TARGET_OPCODE(G_SPLAT_VECTOR)
+/// Generic stepvector.
+HANDLE_TARGET_OPCODE(G_STEP_VECTOR)
+
/// Generic masked compress.
HANDLE_TARGET_OPCODE(G_VECTOR_COMPRESS)
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index 62bb9789afe5d2..60606db078b374 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -1590,6 +1590,13 @@ def G_SPLAT_VECTOR: GenericInstruction {
let hasSideEffects = false;
}
+// Generic stepvector.
+def G_STEP_VECTOR: GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins unknown:$step);
+ let hasSideEffects = false;
+}
+
// Generic masked compress.
def G_VECTOR_COMPRESS: GenericInstruction {
let OutOperandList = (outs type0:$dst);
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 02dbe781babdba..a8836eef0c1813 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -809,9 +809,23 @@ MachineInstrBuilder MachineIRBuilder::buildInsert(const DstOp &Res,
return buildInstr(TargetOpcode::G_INSERT, Res, {Src, Op, uint64_t(Index)});
}
+MachineInstrBuilder MachineIRBuilder::buildStepVector(const DstOp &Res,
+ const APInt &Step) {
+ ConstantInt *CI = ConstantInt::get(getMF().getFunction().getContext(), Step);
+ return buildStepVector(Res, *CI);
+}
+
+MachineInstrBuilder MachineIRBuilder::buildStepVector(const DstOp &Res,
+ const ConstantInt &Step) {
+ auto StepVector = buildInstr(TargetOpcode::G_STEP_VECTOR);
+ StepVector->setDebugLoc(DebugLoc());
+ Res.addDefToMIB(*getMRI(), StepVector);
+ StepVector.addCImm(&Step);
+ return StepVector;
+}
+
MachineInstrBuilder MachineIRBuilder::buildVScale(const DstOp &Res,
unsigned MinElts) {
-
auto IntN = IntegerType::get(getMF().getFunction().getContext(),
Res.getLLTTy(*getMRI()).getScalarSizeInBits());
ConstantInt *CI = ConstantInt::get(IntN, MinElts);
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index e2c09fe25d55cd..b13c6abb26ccd1 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1729,6 +1729,36 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
}
break;
}
+ case TargetOpcode::G_STEP_VECTOR: {
+ if (!MI->getOperand(1).isCImm()) {
+ report("operand must be cimm", MI);
+ break;
+ }
+
+ if (!MI->getOperand(1).getCImm()->getValue().isStrictlyPositive()) {
+ report("step must be >= 0", MI);
+ break;
+ }
+
+ LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
+ if (!DstTy.isScalableVector()) {
+ report("Destination type must be a scalable vector", MI);
+ break;
+ }
+
+ // <vscale x 2 x p0>
+ if (!DstTy.getElementType().isScalar()) {
+ report("Destination element type must be scalar", MI);
+ break;
+ }
+
+ if (MI->getOperand(1).getCImm()->getBitWidth() !=
+ DstTy.getElementType().getScalarSizeInBits()) {
+ report("step bitwidth differs from result type element bitwidth", MI);
+ break;
+ }
+ break;
+ }
case TargetOpcode::G_INSERT_SUBVECTOR: {
const MachineOperand &Src0Op = MI->getOperand(1);
if (!Src0Op.isReg()) {
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index 6be99d0088f1cb..f4c702c50ca774 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -665,6 +665,9 @@
# DEBUG-NEXT: G_SPLAT_VECTOR (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: G_STEP_VECTOR (opcode 236): 2 type indices, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: G_VECTOR_COMPRESS (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
diff --git a/llvm/test/MachineVerifier/test_step-vector.mir b/llvm/test/MachineVerifier/test_step-vector.mir
new file mode 100644
index 00000000000000..9065e7fdf39d39
--- /dev/null
+++ b/llvm/test/MachineVerifier/test_step-vector.mir
@@ -0,0 +1,29 @@
+# RUN: not --crash llc -verify-machineinstrs -mtriple=arm64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# REQUIRES: aarch64-registered-target
+
+---
+name: g_step_vector
+body: |
+ bb.0:
+
+ %0:_(s32) = G_CONSTANT i32 4
+
+ ; CHECK: operand must be cimm
+ %1:_(s32) = G_STEP_VECTOR %0
+
+ ; CHECK: step must be >= 0
+ %2:_(s32) = G_STEP_VECTOR i32 -1
+
+ ; CHECK: Destination type must be a scalable vector
+ %3:_(<4 x s64>) = G_STEP_VECTOR i32 5
+
+ ; CHECK: Destination element type must be scalar
+ %4:_(<vscale x 4 x p0>) = G_STEP_VECTOR i32 9
+
+ ; CHECK: step bitwidth differs from result type element bitwidth
+ %6:_(<vscale x 2 x s33>) = G_STEP_VECTOR i32 56
+
+ %7:_(<vscale x 2 x s128>) = G_STEP_VECTOR i128 79
+
+...
+
>From bc522d167f27c820d7765cb3e6ef9b099ff79b69 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= <schuett at gmail.com>
Date: Sat, 9 Nov 2024 17:13:43 +0100
Subject: [PATCH 2/7] small fixes
---
llvm/docs/GlobalISel/GenericOpcode.rst | 2 +-
llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/docs/GlobalISel/GenericOpcode.rst b/llvm/docs/GlobalISel/GenericOpcode.rst
index b360d4ba35b80e..f443012e705fd0 100644
--- a/llvm/docs/GlobalISel/GenericOpcode.rst
+++ b/llvm/docs/GlobalISel/GenericOpcode.rst
@@ -754,7 +754,7 @@ type. If the operand is larger than the vector element type, the scalar is
implicitly truncated to the vector element type.
G_STEP_VECTOR
-^^^^^^^^^^^^^^^^
+^^^^^^^^^^^^^
Create a scalable vector where all lanes are linear sequences starting at 0
with a given unsigned step.
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index a8836eef0c1813..90650c905541a6 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -834,6 +834,7 @@ MachineInstrBuilder MachineIRBuilder::buildVScale(const DstOp &Res,
MachineInstrBuilder MachineIRBuilder::buildVScale(const DstOp &Res,
const ConstantInt &MinElts) {
+
auto VScale = buildInstr(TargetOpcode::G_VSCALE);
VScale->setDebugLoc(DebugLoc());
Res.addDefToMIB(*getMRI(), VScale);
>From 7af4bb4ac4a2927ba7a6f7d63a5820e689b04c43 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= <schuett at gmail.com>
Date: Sat, 9 Nov 2024 17:14:46 +0100
Subject: [PATCH 3/7] white space
---
llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 90650c905541a6..a150321fe7a989 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -826,6 +826,7 @@ MachineInstrBuilder MachineIRBuilder::buildStepVector(const DstOp &Res,
MachineInstrBuilder MachineIRBuilder::buildVScale(const DstOp &Res,
unsigned MinElts) {
+
auto IntN = IntegerType::get(getMF().getFunction().getContext(),
Res.getLLTTy(*getMRI()).getScalarSizeInBits());
ConstantInt *CI = ConstantInt::get(IntN, MinElts);
@@ -834,7 +835,6 @@ MachineInstrBuilder MachineIRBuilder::buildVScale(const DstOp &Res,
MachineInstrBuilder MachineIRBuilder::buildVScale(const DstOp &Res,
const ConstantInt &MinElts) {
-
auto VScale = buildInstr(TargetOpcode::G_VSCALE);
VScale->setDebugLoc(DebugLoc());
Res.addDefToMIB(*getMRI(), VScale);
>From 409804c9fb3dd173f3d27db1d43cbe39586fd3f3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= <schuett at gmail.com>
Date: Sat, 9 Nov 2024 18:02:41 +0100
Subject: [PATCH 4/7] fix validation
---
.../CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index f4c702c50ca774..4fea713ee4c32c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -665,7 +665,7 @@
# DEBUG-NEXT: G_SPLAT_VECTOR (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: G_STEP_VECTOR (opcode 236): 2 type indices, 0 imm indices
+# DEBUG-NEXT: G_STEP_VECTOR (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: G_VECTOR_COMPRESS (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
>From b30e28647dbe54c0b24757ce4c98cb57ac0a40b9 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= <schuett at gmail.com>
Date: Sun, 10 Nov 2024 07:17:29 +0100
Subject: [PATCH 5/7] address review comments
---
.../llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 14 +-------------
llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 11 ++++-------
2 files changed, 5 insertions(+), 20 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index 37ea9c4b9a124f..05e3db7167fa4a 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -1181,19 +1181,7 @@ class MachineIRBuilder {
/// \pre \p Res must be a generic virtual register with scalar type.
///
/// \return a MachineInstrBuilder for the newly created instruction.
- MachineInstrBuilder buildStepVector(const DstOp &Res,
- const ConstantInt &Step);
-
- /// Build and insert \p Res = G_STEP_VECTOR \p Step
- ///
- /// G_STEP_VECTOR returns a scalable vector of linear sequence of step \p Step
- /// into \p Res.
- ///
- /// \pre setBasicBlock or setMI must have been called.
- /// \pre \p Res must be a generic virtual register with scalar type.
- ///
- /// \return a MachineInstrBuilder for the newly created instruction.
- MachineInstrBuilder buildStepVector(const DstOp &Res, const APInt &Step);
+ MachineInstrBuilder buildStepVector(const DstOp &Res, unsigned Step);
/// Build and insert \p Res = G_VSCALE \p MinElts
///
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index a150321fe7a989..6eb1c6900fd09b 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -810,17 +810,14 @@ MachineInstrBuilder MachineIRBuilder::buildInsert(const DstOp &Res,
}
MachineInstrBuilder MachineIRBuilder::buildStepVector(const DstOp &Res,
- const APInt &Step) {
- ConstantInt *CI = ConstantInt::get(getMF().getFunction().getContext(), Step);
- return buildStepVector(Res, *CI);
-}
+ unsigned Step) {
+ ConstantInt *CI =
+ ConstantInt::get(getMF().getFunction().getContext(), APInt(64, Step));
-MachineInstrBuilder MachineIRBuilder::buildStepVector(const DstOp &Res,
- const ConstantInt &Step) {
auto StepVector = buildInstr(TargetOpcode::G_STEP_VECTOR);
StepVector->setDebugLoc(DebugLoc());
Res.addDefToMIB(*getMRI(), StepVector);
- StepVector.addCImm(&Step);
+ StepVector.addCImm(CI);
return StepVector;
}
>From 0a0c98722b1a09bf3d7cd2614bd35ec70bfc1cb7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= <schuett at gmail.com>
Date: Sun, 10 Nov 2024 07:52:08 +0100
Subject: [PATCH 6/7] docs + >= -> >
---
llvm/docs/GlobalISel/GenericOpcode.rst | 3 ++-
llvm/lib/CodeGen/MachineVerifier.cpp | 2 +-
llvm/test/MachineVerifier/test_step-vector.mir | 2 +-
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/llvm/docs/GlobalISel/GenericOpcode.rst b/llvm/docs/GlobalISel/GenericOpcode.rst
index f443012e705fd0..e2911ed7838772 100644
--- a/llvm/docs/GlobalISel/GenericOpcode.rst
+++ b/llvm/docs/GlobalISel/GenericOpcode.rst
@@ -759,7 +759,8 @@ G_STEP_VECTOR
Create a scalable vector where all lanes are linear sequences starting at 0
with a given unsigned step.
-The type of the operand must be equal to the vector element type.
+The type of the operand must be equal to the vector element type. Arithmetic
+is performed modulo the bitwidth of the element.
.. code-block::
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index b13c6abb26ccd1..4cdc879c73c7eb 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1736,7 +1736,7 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
}
if (!MI->getOperand(1).getCImm()->getValue().isStrictlyPositive()) {
- report("step must be >= 0", MI);
+ report("step must be > 0", MI);
break;
}
diff --git a/llvm/test/MachineVerifier/test_step-vector.mir b/llvm/test/MachineVerifier/test_step-vector.mir
index 9065e7fdf39d39..b4a01bb258da10 100644
--- a/llvm/test/MachineVerifier/test_step-vector.mir
+++ b/llvm/test/MachineVerifier/test_step-vector.mir
@@ -11,7 +11,7 @@ body: |
; CHECK: operand must be cimm
%1:_(s32) = G_STEP_VECTOR %0
- ; CHECK: step must be >= 0
+ ; CHECK: step must be > 0
%2:_(s32) = G_STEP_VECTOR i32 -1
; CHECK: Destination type must be a scalable vector
>From bb5ed03bebbd711f184158ca8deeddd49d4b3732 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= <schuett at gmail.com>
Date: Sun, 10 Nov 2024 08:31:57 +0100
Subject: [PATCH 7/7] fix type
---
llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index 05e3db7167fa4a..3516065f9b6cb3 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -1178,7 +1178,7 @@ class MachineIRBuilder {
/// into \p Res.
///
/// \pre setBasicBlock or setMI must have been called.
- /// \pre \p Res must be a generic virtual register with scalar type.
+ /// \pre \p Res must be a generic virtual register with scalable vector type.
///
/// \return a MachineInstrBuilder for the newly created instruction.
MachineInstrBuilder buildStepVector(const DstOp &Res, unsigned Step);
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