[llvm] [M68k] Add remaining addressing modes for Atomic operations (PR #115523)

[John Paul Adrian Glaubitz via llvm-commits]

glaubitz wrote:

The backend still seems to have problems to select certain atomic instructions:

```
rustc-LLVM ERROR: Cannot select: t14: ch = AtomicStore<(store unordered (s8) into %ir.25)> t13:1, t13, t9
  t13: i8,ch = AtomicLoad<(load unordered (s8) from %ir.26)> t0, t12
    t12: i32 = add t11, t2
      t11: i32,ch = CopyFromReg t0, Register:i32 %0
        t10: i32 = Register %0
      t2: i32,ch = CopyFromReg t0, Register:i32 %8
        t1: i32 = Register %8
  t9: i32 = add t8, t2
    t8: i32,ch = CopyFromReg t0, Register:i32 %1
      t7: i32 = Register %1
    t2: i32,ch = CopyFromReg t0, Register:i32 %8
      t1: i32 = Register %8
In function: __llvm_memmove_element_unordered_atomic_1
error: rustc interrupted by SIGSEGV, printing backtrace
```

https://github.com/llvm/llvm-project/pull/115523