[llvm] AMDGPU/GlobalISel: Remove getVRegDef null checks in selector (PR #115530)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 8 10:29:28 PST 2024
https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/115530
We should be able to assume every virtual register is defined.
>From ea9c26481d116fa37fd41460a5b0f68947bd9359 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Fri, 18 Oct 2024 22:31:51 +0400
Subject: [PATCH] AMDGPU/GlobalISel: Remove getVRegDef null checks in selector
We should be able to assume every virtual register is defined.
---
.../AMDGPU/AMDGPUInstructionSelector.cpp | 42 ++++++++-----------
1 file changed, 18 insertions(+), 24 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 1873251ea358b1..d1e29cd4618371 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -3839,7 +3839,7 @@ AMDGPUInstructionSelector::selectVOP3PModsImpl(
unsigned Mods = 0;
MachineInstr *MI = MRI.getVRegDef(Src);
- if (MI && MI->getOpcode() == AMDGPU::G_FNEG &&
+ if (MI->getOpcode() == AMDGPU::G_FNEG &&
// It's possible to see an f32 fneg here, but unlikely.
// TODO: Treat f32 fneg as only high bit.
MRI.getType(Src) == LLT::fixed_vector(2, 16)) {
@@ -4662,24 +4662,24 @@ AMDGPUInstructionSelector::selectMUBUFScratchOffen(MachineOperand &Root) const {
// offsets.
std::optional<int> FI;
Register VAddr = Root.getReg();
- if (const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg())) {
- Register PtrBase;
- int64_t ConstOffset;
- std::tie(PtrBase, ConstOffset) = getPtrBaseWithConstantOffset(VAddr, *MRI);
- if (ConstOffset != 0) {
- if (TII.isLegalMUBUFImmOffset(ConstOffset) &&
- (!STI.privateMemoryResourceIsRangeChecked() ||
- KB->signBitIsZero(PtrBase))) {
- const MachineInstr *PtrBaseDef = MRI->getVRegDef(PtrBase);
- if (PtrBaseDef->getOpcode() == AMDGPU::G_FRAME_INDEX)
- FI = PtrBaseDef->getOperand(1).getIndex();
- else
- VAddr = PtrBase;
- Offset = ConstOffset;
- }
- } else if (RootDef->getOpcode() == AMDGPU::G_FRAME_INDEX) {
- FI = RootDef->getOperand(1).getIndex();
+
+ const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg());
+ Register PtrBase;
+ int64_t ConstOffset;
+ std::tie(PtrBase, ConstOffset) = getPtrBaseWithConstantOffset(VAddr, *MRI);
+ if (ConstOffset != 0) {
+ if (TII.isLegalMUBUFImmOffset(ConstOffset) &&
+ (!STI.privateMemoryResourceIsRangeChecked() ||
+ KB->signBitIsZero(PtrBase))) {
+ const MachineInstr *PtrBaseDef = MRI->getVRegDef(PtrBase);
+ if (PtrBaseDef->getOpcode() == AMDGPU::G_FRAME_INDEX)
+ FI = PtrBaseDef->getOperand(1).getIndex();
+ else
+ VAddr = PtrBase;
+ Offset = ConstOffset;
}
+ } else if (RootDef->getOpcode() == AMDGPU::G_FRAME_INDEX) {
+ FI = RootDef->getOperand(1).getIndex();
}
return {{[=](MachineInstrBuilder &MIB) { // rsrc
@@ -4901,9 +4901,6 @@ AMDGPUInstructionSelector::selectMUBUFScratchOffset(
std::pair<Register, unsigned>
AMDGPUInstructionSelector::selectDS1Addr1OffsetImpl(MachineOperand &Root) const {
const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg());
- if (!RootDef)
- return std::pair(Root.getReg(), 0);
-
int64_t ConstAddr = 0;
Register PtrBase;
@@ -4966,9 +4963,6 @@ std::pair<Register, unsigned>
AMDGPUInstructionSelector::selectDSReadWrite2Impl(MachineOperand &Root,
unsigned Size) const {
const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg());
- if (!RootDef)
- return std::pair(Root.getReg(), 0);
-
int64_t ConstAddr = 0;
Register PtrBase;
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