[llvm] [RISCV] Set a barrier between mask producer and user of V0 (PR #114012)

[Philip Reames via llvm-commits]

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@@ -0,0 +1,119 @@
+//===- RISCVVectorMaskDAGMutation.cpp - RISCV Vector Mask DAGMutation -----===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// A schedule mutation that add a dependency between masks producing
+// instructions and masked instructions, so that we will not extend the live
+// interval of mask register.
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preames wrote:

Can you expand this comment to include the bit about why we don't just have a single register register class for this purpose, and that this is basically a workaround for that?  (i.e. what you said on the review)

https://github.com/llvm/llvm-project/pull/114012