[llvm] [RISCV] Only allow 5 bit shift amounts in disassembler for RV32. (PR #115432)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Fri Nov 8 09:12:32 PST 2024

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https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/115432

Previous message: [llvm] [RISCV] Only allow 5 bit shift amounts in disassembler for RV32. (PR #115432)
Next message: [clang] [clang-tools-extra] [llvm] Add code completion for C++20 keywords. (PR #107982)
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