[llvm] 231e03b - [AArch64] Add select-opt test with select transformed to cast.
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 8 05:08:58 PST 2024
Author: Florian Hahn
Date: 2024-11-08T13:07:38Z
New Revision: 231e03ba7e82896847dbc27d457dbb208f04699c
URL: https://github.com/llvm/llvm-project/commit/231e03ba7e82896847dbc27d457dbb208f04699c
DIFF: https://github.com/llvm/llvm-project/commit/231e03ba7e82896847dbc27d457dbb208f04699c.diff
LOG: [AArch64] Add select-opt test with select transformed to cast.
Add tests with add and sub binops with zext i1 operands.
Added:
llvm/test/CodeGen/AArch64/selectopt-cast.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/selectopt-cast.ll b/llvm/test/CodeGen/AArch64/selectopt-cast.ll
new file mode 100644
index 00000000000000..b1804a02ec1c82
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/selectopt-cast.ll
@@ -0,0 +1,605 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -select-optimize -mtriple=arm64-apple-macosx-mcpu=apple-m4 -S %s | FileCheck %s
+; RUN: opt -passes='require<profile-summary>,function(select-optimize)' -mtriple=arm64-apple-macosx-mcpu=apple-m4 -S %s | FileCheck %s
+
+define void @test_add_zext(ptr %dst, ptr %src, i64 %j.start, i64 %p, i64 %i.start) {
+; CHECK-LABEL: @test_add_zext(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[HIGH:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[LOOP]] ]
+; CHECK-NEXT: [[GEP_I:%.*]] = getelementptr inbounds ptr, ptr [[SRC:%.*]], i64 [[I]]
+; CHECK-NEXT: [[L_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
+; CHECK-NEXT: [[GEP_J:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[J]]
+; CHECK-NEXT: [[L_J:%.*]] = load ptr, ptr [[GEP_J]], align 8
+; CHECK-NEXT: [[CMP3:%.*]] = icmp ult ptr [[L_I]], [[L_J]]
+; CHECK-NEXT: [[DEC:%.*]] = zext i1 [[CMP3]] to i64
+; CHECK-NEXT: [[J_NEXT]] = add nsw i64 [[J]], [[DEC]]
+; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
+; CHECK-NEXT: store i64 [[J_NEXT]], ptr [[GEP_DST]], align 8
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV]], [[HIGH]]
+; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[EXIT:%.*]], label [[LOOP]]
+; CHECK: exit:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %j = phi i64 [ %j.start, %entry ], [ %j.next, %loop ]
+ %i = phi i64 [ %i.start, %entry ], [ %j.next, %loop ]
+ %gep.i = getelementptr inbounds ptr, ptr %src, i64 %i
+ %l.i = load ptr, ptr %gep.i, align 8
+ %gep.j = getelementptr inbounds ptr, ptr %src, i64 %j
+ %l.j = load ptr, ptr %gep.j, align 8
+ %cmp3 = icmp ult ptr %l.i, %l.j
+ %dec = zext i1 %cmp3 to i64
+ %j.next = add nsw i64 %j, %dec
+ %gep.dst = getelementptr inbounds ptr, ptr %dst, i64 %iv
+ store i64 %j.next, ptr %gep.dst, align 8
+ %iv.next = add i64 %iv, 1
+ %ec = icmp eq i64 %iv, %j.start
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+define void @test_add_zext_not(ptr %dst, ptr %src, i64 %j.start, i64 %p, i64 %i.start) {
+; CHECK-LABEL: @test_add_zext_not(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[HIGH:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[LOOP]] ]
+; CHECK-NEXT: [[GEP_I:%.*]] = getelementptr inbounds ptr, ptr [[SRC:%.*]], i64 [[I]]
+; CHECK-NEXT: [[L_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
+; CHECK-NEXT: [[GEP_J:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[J]]
+; CHECK-NEXT: [[L_J:%.*]] = load ptr, ptr [[GEP_J]], align 8
+; CHECK-NEXT: [[CMP3:%.*]] = icmp ult ptr [[L_I]], [[L_J]]
+; CHECK-NEXT: [[NOT_CMP3:%.*]] = xor i1 [[CMP3]], true
+; CHECK-NEXT: [[DEC:%.*]] = zext i1 [[NOT_CMP3]] to i64
+; CHECK-NEXT: [[J_NEXT]] = add nsw i64 [[J]], [[DEC]]
+; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
+; CHECK-NEXT: store i64 [[J_NEXT]], ptr [[GEP_DST]], align 8
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV]], [[HIGH]]
+; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[EXIT:%.*]], label [[LOOP]]
+; CHECK: exit:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %j = phi i64 [ %j.start, %entry ], [ %j.next, %loop ]
+ %i = phi i64 [ %i.start, %entry ], [ %j.next, %loop ]
+ %gep.i = getelementptr inbounds ptr, ptr %src, i64 %i
+ %l.i = load ptr, ptr %gep.i, align 8
+ %gep.j = getelementptr inbounds ptr, ptr %src, i64 %j
+ %l.j = load ptr, ptr %gep.j, align 8
+ %cmp3 = icmp ult ptr %l.i, %l.j
+ %not.cmp3 = xor i1 %cmp3, true
+ %dec = zext i1 %not.cmp3 to i64
+ %j.next = add nsw i64 %j, %dec
+ %gep.dst = getelementptr inbounds ptr, ptr %dst, i64 %iv
+ store i64 %j.next, ptr %gep.dst, align 8
+ %iv.next = add i64 %iv, 1
+ %ec = icmp eq i64 %iv, %j.start
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+define void @test_add_sext(ptr %dst, ptr %src, i64 %j.start, i64 %p, i64 %i.start) {
+; CHECK-LABEL: @test_add_sext(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[HIGH:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[LOOP]] ]
+; CHECK-NEXT: [[GEP_I:%.*]] = getelementptr inbounds ptr, ptr [[SRC:%.*]], i64 [[I]]
+; CHECK-NEXT: [[L_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
+; CHECK-NEXT: [[GEP_J:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[J]]
+; CHECK-NEXT: [[L_J:%.*]] = load ptr, ptr [[GEP_J]], align 8
+; CHECK-NEXT: [[CMP3:%.*]] = icmp ult ptr [[L_I]], [[L_J]]
+; CHECK-NEXT: [[DEC:%.*]] = sext i1 [[CMP3]] to i64
+; CHECK-NEXT: [[J_NEXT]] = add nsw i64 [[J]], [[DEC]]
+; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
+; CHECK-NEXT: store i64 [[J_NEXT]], ptr [[GEP_DST]], align 8
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV]], [[HIGH]]
+; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[EXIT:%.*]], label [[LOOP]]
+; CHECK: exit:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %j = phi i64 [ %j.start, %entry ], [ %j.next, %loop ]
+ %i = phi i64 [ %i.start, %entry ], [ %j.next, %loop ]
+ %gep.i = getelementptr inbounds ptr, ptr %src, i64 %i
+ %l.i = load ptr, ptr %gep.i, align 8
+ %gep.j = getelementptr inbounds ptr, ptr %src, i64 %j
+ %l.j = load ptr, ptr %gep.j, align 8
+ %cmp3 = icmp ult ptr %l.i, %l.j
+ %dec = sext i1 %cmp3 to i64
+ %j.next = add nsw i64 %j, %dec
+ %gep.dst = getelementptr inbounds ptr, ptr %dst, i64 %iv
+ store i64 %j.next, ptr %gep.dst, align 8
+ %iv.next = add i64 %iv, 1
+ %ec = icmp eq i64 %iv, %j.start
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+define void @test_add_sext_not(ptr %dst, ptr %src, i64 %j.start, i64 %p, i64 %i.start) {
+; CHECK-LABEL: @test_add_sext_not(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[HIGH:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[LOOP]] ]
+; CHECK-NEXT: [[GEP_I:%.*]] = getelementptr inbounds ptr, ptr [[SRC:%.*]], i64 [[I]]
+; CHECK-NEXT: [[L_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
+; CHECK-NEXT: [[GEP_J:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[J]]
+; CHECK-NEXT: [[L_J:%.*]] = load ptr, ptr [[GEP_J]], align 8
+; CHECK-NEXT: [[CMP3:%.*]] = icmp ult ptr [[L_I]], [[L_J]]
+; CHECK-NEXT: [[NOT_CMP3:%.*]] = xor i1 [[CMP3]], true
+; CHECK-NEXT: [[DEC:%.*]] = sext i1 [[NOT_CMP3]] to i64
+; CHECK-NEXT: [[J_NEXT]] = add nsw i64 [[J]], [[DEC]]
+; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
+; CHECK-NEXT: store i64 [[J_NEXT]], ptr [[GEP_DST]], align 8
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV]], [[HIGH]]
+; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[EXIT:%.*]], label [[LOOP]]
+; CHECK: exit:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %j = phi i64 [ %j.start, %entry ], [ %j.next, %loop ]
+ %i = phi i64 [ %i.start, %entry ], [ %j.next, %loop ]
+ %gep.i = getelementptr inbounds ptr, ptr %src, i64 %i
+ %l.i = load ptr, ptr %gep.i, align 8
+ %gep.j = getelementptr inbounds ptr, ptr %src, i64 %j
+ %l.j = load ptr, ptr %gep.j, align 8
+ %cmp3 = icmp ult ptr %l.i, %l.j
+ %not.cmp3 = xor i1 %cmp3, true
+ %dec = sext i1 %not.cmp3 to i64
+ %j.next = add nsw i64 %j, %dec
+ %gep.dst = getelementptr inbounds ptr, ptr %dst, i64 %iv
+ store i64 %j.next, ptr %gep.dst, align 8
+ %iv.next = add i64 %iv, 1
+ %ec = icmp eq i64 %iv, %j.start
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+define void @test_add_sext_not_and_regular_select(ptr %dst, ptr %src, i64 %j.start, i64 %p, i64 %i.start) {
+; CHECK-LABEL: @test_add_sext_not_and_regular_select(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[HIGH:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[LOOP]] ]
+; CHECK-NEXT: [[GEP_I:%.*]] = getelementptr inbounds ptr, ptr [[SRC:%.*]], i64 [[I]]
+; CHECK-NEXT: [[L_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
+; CHECK-NEXT: [[GEP_J:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[J]]
+; CHECK-NEXT: [[L_J:%.*]] = load ptr, ptr [[GEP_J]], align 8
+; CHECK-NEXT: [[CMP3:%.*]] = icmp ult ptr [[L_I]], [[L_J]]
+; CHECK-NEXT: [[NOT_CMP3:%.*]] = xor i1 [[CMP3]], true
+; CHECK-NEXT: [[DEC:%.*]] = sext i1 [[NOT_CMP3]] to i64
+; CHECK-NEXT: [[J_NEXT]] = add nsw i64 [[J]], [[DEC]]
+; CHECK-NEXT: [[SINK:%.*]] = select i1 [[CMP3]], ptr [[L_I]], ptr [[L_J]]
+; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
+; CHECK-NEXT: store ptr [[SINK]], ptr [[GEP_DST]], align 8
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV]], [[HIGH]]
+; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[EXIT:%.*]], label [[LOOP]]
+; CHECK: exit:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %j = phi i64 [ %j.start, %entry ], [ %j.next, %loop ]
+ %i = phi i64 [ %i.start, %entry ], [ %j.next, %loop ]
+ %gep.i = getelementptr inbounds ptr, ptr %src, i64 %i
+ %l.i = load ptr, ptr %gep.i, align 8
+ %gep.j = getelementptr inbounds ptr, ptr %src, i64 %j
+ %l.j = load ptr, ptr %gep.j, align 8
+ %cmp3 = icmp ult ptr %l.i, %l.j
+ %not.cmp3 = xor i1 %cmp3, true
+ %dec = sext i1 %not.cmp3 to i64
+ %j.next = add nsw i64 %j, %dec
+ %sink = select i1 %cmp3, ptr %l.i, ptr %l.j
+ %gep.dst = getelementptr inbounds ptr, ptr %dst, i64 %iv
+ store ptr %sink, ptr %gep.dst, align 8
+ %iv.next = add i64 %iv, 1
+ %ec = icmp eq i64 %iv, %j.start
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+define void @test_add_sext_not_and_regular_select2(ptr %dst, ptr %src, i64 %j.start, i64 %p, i64 %i.start) {
+; CHECK-LABEL: @test_add_sext_not_and_regular_select2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[HIGH:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[LOOP]] ]
+; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds ptr, ptr [[SRC:%.*]], i64 [[I]]
+; CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX1]], align 8
+; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[J]]
+; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[ARRAYIDX2]], align 8
+; CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 [[P:%.*]]
+; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[ARRAYIDX_I]], align 8
+; CHECK-NEXT: [[ARRAYIDX1_I:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 [[P]]
+; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[ARRAYIDX1_I]], align 8
+; CHECK-NEXT: [[CMP3:%.*]] = icmp slt i64 [[TMP2]], [[TMP3]]
+; CHECK-NEXT: [[DOTSINK:%.*]] = select i1 [[CMP3]], ptr [[TMP0]], ptr [[TMP1]]
+; CHECK-NEXT: [[NOT_CMP3:%.*]] = xor i1 [[CMP3]], true
+; CHECK-NEXT: [[DEC:%.*]] = sext i1 [[NOT_CMP3]] to i64
+; CHECK-NEXT: [[J_NEXT]] = add nsw i64 [[J]], [[DEC]]
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
+; CHECK-NEXT: store ptr [[DOTSINK]], ptr [[TMP4]], align 8
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV]], [[HIGH]]
+; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[EXIT:%.*]], label [[LOOP]]
+; CHECK: exit:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %j = phi i64 [ %j.start, %entry ], [ %j.next, %loop ]
+ %i = phi i64 [ %i.start, %entry ], [ %j.next, %loop ]
+ %gep.i = getelementptr inbounds ptr, ptr %src, i64 %i
+ %l.gep.i = load ptr, ptr %gep.i, align 8
+ %gep.j = getelementptr inbounds ptr, ptr %src, i64 %j
+ %l.gep.j = load ptr, ptr %gep.j, align 8
+ %gep.i.1 = getelementptr inbounds i64, ptr %l.gep.i, i64 %p
+ %2 = load i64, ptr %gep.i.1, align 8
+ %gep.j.1 = getelementptr inbounds i64, ptr %l.gep.j, i64 %p
+ %3 = load i64, ptr %gep.j.1, align 8
+ %cmp3 = icmp slt i64 %2, %3
+ %sel = select i1 %cmp3, ptr %l.gep.i, ptr %l.gep.j
+ %not.cmp3 = xor i1 %cmp3, true
+ %dec = sext i1 %not.cmp3 to i64
+ %j.next = add nsw i64 %j, %dec
+ %gep.dst = getelementptr inbounds ptr, ptr %dst, i64 %iv
+ store ptr %sel, ptr %gep.dst, align 8
+ %iv.next = add i64 %iv, 1
+ %ec = icmp eq i64 %iv, %j.start
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+define void @test_sub_zext(ptr %dst, ptr %src, i64 %j.start, i64 %p, i64 %i.start) {
+; CHECK-LABEL: @test_sub_zext(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[HIGH:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[LOOP]] ]
+; CHECK-NEXT: [[GEP_I:%.*]] = getelementptr inbounds ptr, ptr [[SRC:%.*]], i64 [[I]]
+; CHECK-NEXT: [[L_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
+; CHECK-NEXT: [[GEP_J:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[J]]
+; CHECK-NEXT: [[L_J:%.*]] = load ptr, ptr [[GEP_J]], align 8
+; CHECK-NEXT: [[CMP3:%.*]] = icmp ult ptr [[L_I]], [[L_J]]
+; CHECK-NEXT: [[DEC:%.*]] = zext i1 [[CMP3]] to i64
+; CHECK-NEXT: [[J_NEXT]] = sub nsw i64 [[J]], [[DEC]]
+; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
+; CHECK-NEXT: store i64 [[J_NEXT]], ptr [[GEP_DST]], align 8
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV]], [[HIGH]]
+; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[EXIT:%.*]], label [[LOOP]]
+; CHECK: exit:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %j = phi i64 [ %j.start, %entry ], [ %j.next, %loop ]
+ %i = phi i64 [ %i.start, %entry ], [ %j.next, %loop ]
+ %gep.i = getelementptr inbounds ptr, ptr %src, i64 %i
+ %l.i = load ptr, ptr %gep.i, align 8
+ %gep.j = getelementptr inbounds ptr, ptr %src, i64 %j
+ %l.j = load ptr, ptr %gep.j, align 8
+ %cmp3 = icmp ult ptr %l.i, %l.j
+ %dec = zext i1 %cmp3 to i64
+ %j.next = sub nsw i64 %j, %dec
+ %gep.dst = getelementptr inbounds ptr, ptr %dst, i64 %iv
+ store i64 %j.next, ptr %gep.dst, align 8
+ %iv.next = add i64 %iv, 1
+ %ec = icmp eq i64 %iv, %j.start
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+define void @test_sub_zext_not(ptr %dst, ptr %src, i64 %j.start, i64 %p, i64 %i.start) {
+; CHECK-LABEL: @test_sub_zext_not(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[HIGH:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[LOOP]] ]
+; CHECK-NEXT: [[GEP_I:%.*]] = getelementptr inbounds ptr, ptr [[SRC:%.*]], i64 [[I]]
+; CHECK-NEXT: [[L_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
+; CHECK-NEXT: [[GEP_J:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[J]]
+; CHECK-NEXT: [[L_J:%.*]] = load ptr, ptr [[GEP_J]], align 8
+; CHECK-NEXT: [[CMP3:%.*]] = icmp ult ptr [[L_I]], [[L_J]]
+; CHECK-NEXT: [[NOT_CMP3:%.*]] = xor i1 [[CMP3]], true
+; CHECK-NEXT: [[DEC:%.*]] = zext i1 [[NOT_CMP3]] to i64
+; CHECK-NEXT: [[J_NEXT]] = sub nsw i64 [[J]], [[DEC]]
+; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
+; CHECK-NEXT: store i64 [[J_NEXT]], ptr [[GEP_DST]], align 8
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV]], [[HIGH]]
+; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[EXIT:%.*]], label [[LOOP]]
+; CHECK: exit:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %j = phi i64 [ %j.start, %entry ], [ %j.next, %loop ]
+ %i = phi i64 [ %i.start, %entry ], [ %j.next, %loop ]
+ %gep.i = getelementptr inbounds ptr, ptr %src, i64 %i
+ %l.i = load ptr, ptr %gep.i, align 8
+ %gep.j = getelementptr inbounds ptr, ptr %src, i64 %j
+ %l.j = load ptr, ptr %gep.j, align 8
+ %cmp3 = icmp ult ptr %l.i, %l.j
+ %not.cmp3 = xor i1 %cmp3, true
+ %dec = zext i1 %not.cmp3 to i64
+ %j.next = sub nsw i64 %j, %dec
+ %gep.dst = getelementptr inbounds ptr, ptr %dst, i64 %iv
+ store i64 %j.next, ptr %gep.dst, align 8
+ %iv.next = add i64 %iv, 1
+ %ec = icmp eq i64 %iv, %j.start
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+define void @test_sub_sext(ptr %dst, ptr %src, i64 %j.start, i64 %p, i64 %i.start) {
+; CHECK-LABEL: @test_sub_sext(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[HIGH:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[LOOP]] ]
+; CHECK-NEXT: [[GEP_I:%.*]] = getelementptr inbounds ptr, ptr [[SRC:%.*]], i64 [[I]]
+; CHECK-NEXT: [[L_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
+; CHECK-NEXT: [[GEP_J:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[J]]
+; CHECK-NEXT: [[L_J:%.*]] = load ptr, ptr [[GEP_J]], align 8
+; CHECK-NEXT: [[CMP3:%.*]] = icmp ult ptr [[L_I]], [[L_J]]
+; CHECK-NEXT: [[DEC:%.*]] = sext i1 [[CMP3]] to i64
+; CHECK-NEXT: [[J_NEXT]] = sub nsw i64 [[J]], [[DEC]]
+; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
+; CHECK-NEXT: store i64 [[J_NEXT]], ptr [[GEP_DST]], align 8
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV]], [[HIGH]]
+; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[EXIT:%.*]], label [[LOOP]]
+; CHECK: exit:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %j = phi i64 [ %j.start, %entry ], [ %j.next, %loop ]
+ %i = phi i64 [ %i.start, %entry ], [ %j.next, %loop ]
+ %gep.i = getelementptr inbounds ptr, ptr %src, i64 %i
+ %l.i = load ptr, ptr %gep.i, align 8
+ %gep.j = getelementptr inbounds ptr, ptr %src, i64 %j
+ %l.j = load ptr, ptr %gep.j, align 8
+ %cmp3 = icmp ult ptr %l.i, %l.j
+ %dec = sext i1 %cmp3 to i64
+ %j.next = sub nsw i64 %j, %dec
+ %gep.dst = getelementptr inbounds ptr, ptr %dst, i64 %iv
+ store i64 %j.next, ptr %gep.dst, align 8
+ %iv.next = add i64 %iv, 1
+ %ec = icmp eq i64 %iv, %j.start
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+define void @test_sub_sext_not(ptr %dst, ptr %src, i64 %j.start, i64 %p, i64 %i.start) {
+; CHECK-LABEL: @test_sub_sext_not(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[HIGH:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[LOOP]] ]
+; CHECK-NEXT: [[GEP_I:%.*]] = getelementptr inbounds ptr, ptr [[SRC:%.*]], i64 [[I]]
+; CHECK-NEXT: [[L_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
+; CHECK-NEXT: [[GEP_J:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[J]]
+; CHECK-NEXT: [[L_J:%.*]] = load ptr, ptr [[GEP_J]], align 8
+; CHECK-NEXT: [[CMP3:%.*]] = icmp ult ptr [[L_I]], [[L_J]]
+; CHECK-NEXT: [[NOT_CMP3:%.*]] = xor i1 [[CMP3]], true
+; CHECK-NEXT: [[DEC:%.*]] = sext i1 [[NOT_CMP3]] to i64
+; CHECK-NEXT: [[J_NEXT]] = sub nsw i64 [[J]], [[DEC]]
+; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
+; CHECK-NEXT: store i64 [[J_NEXT]], ptr [[GEP_DST]], align 8
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV]], [[HIGH]]
+; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[EXIT:%.*]], label [[LOOP]]
+; CHECK: exit:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %j = phi i64 [ %j.start, %entry ], [ %j.next, %loop ]
+ %i = phi i64 [ %i.start, %entry ], [ %j.next, %loop ]
+ %gep.i = getelementptr inbounds ptr, ptr %src, i64 %i
+ %l.i = load ptr, ptr %gep.i, align 8
+ %gep.j = getelementptr inbounds ptr, ptr %src, i64 %j
+ %l.j = load ptr, ptr %gep.j, align 8
+ %cmp3 = icmp ult ptr %l.i, %l.j
+ %not.cmp3 = xor i1 %cmp3, true
+ %dec = sext i1 %not.cmp3 to i64
+ %j.next = sub nsw i64 %j, %dec
+ %gep.dst = getelementptr inbounds ptr, ptr %dst, i64 %iv
+ store i64 %j.next, ptr %gep.dst, align 8
+ %iv.next = add i64 %iv, 1
+ %ec = icmp eq i64 %iv, %j.start
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+define void @test_sub_sext_not_and_regular_select(ptr %dst, ptr %src, i64 %j.start, i64 %p, i64 %i.start) {
+; CHECK-LABEL: @test_sub_sext_not_and_regular_select(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[HIGH:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[LOOP]] ]
+; CHECK-NEXT: [[GEP_I:%.*]] = getelementptr inbounds ptr, ptr [[SRC:%.*]], i64 [[I]]
+; CHECK-NEXT: [[L_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
+; CHECK-NEXT: [[GEP_J:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[J]]
+; CHECK-NEXT: [[L_J:%.*]] = load ptr, ptr [[GEP_J]], align 8
+; CHECK-NEXT: [[CMP3:%.*]] = icmp ult ptr [[L_I]], [[L_J]]
+; CHECK-NEXT: [[NOT_CMP3:%.*]] = xor i1 [[CMP3]], true
+; CHECK-NEXT: [[DEC:%.*]] = sext i1 [[NOT_CMP3]] to i64
+; CHECK-NEXT: [[J_NEXT]] = sub nsw i64 [[J]], [[DEC]]
+; CHECK-NEXT: [[SINK:%.*]] = select i1 [[CMP3]], ptr [[L_I]], ptr [[L_J]]
+; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
+; CHECK-NEXT: store ptr [[SINK]], ptr [[GEP_DST]], align 8
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV]], [[HIGH]]
+; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[EXIT:%.*]], label [[LOOP]]
+; CHECK: exit:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %j = phi i64 [ %j.start, %entry ], [ %j.next, %loop ]
+ %i = phi i64 [ %i.start, %entry ], [ %j.next, %loop ]
+ %gep.i = getelementptr inbounds ptr, ptr %src, i64 %i
+ %l.i = load ptr, ptr %gep.i, align 8
+ %gep.j = getelementptr inbounds ptr, ptr %src, i64 %j
+ %l.j = load ptr, ptr %gep.j, align 8
+ %cmp3 = icmp ult ptr %l.i, %l.j
+ %not.cmp3 = xor i1 %cmp3, true
+ %dec = sext i1 %not.cmp3 to i64
+ %j.next = sub nsw i64 %j, %dec
+ %sink = select i1 %cmp3, ptr %l.i, ptr %l.j
+ %gep.dst = getelementptr inbounds ptr, ptr %dst, i64 %iv
+ store ptr %sink, ptr %gep.dst, align 8
+ %iv.next = add i64 %iv, 1
+ %ec = icmp eq i64 %iv, %j.start
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+define void @test_sub_sext_not_and_regular_select2(ptr %dst, ptr %src, i64 %j.start, i64 %p, i64 %i.start) {
+; CHECK-LABEL: @test_sub_sext_not_and_regular_select2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[HIGH:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[LOOP]] ]
+; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds ptr, ptr [[SRC:%.*]], i64 [[I]]
+; CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX1]], align 8
+; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[J]]
+; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[ARRAYIDX2]], align 8
+; CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 [[P:%.*]]
+; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[ARRAYIDX_I]], align 8
+; CHECK-NEXT: [[ARRAYIDX1_I:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 [[P]]
+; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[ARRAYIDX1_I]], align 8
+; CHECK-NEXT: [[CMP3:%.*]] = icmp slt i64 [[TMP2]], [[TMP3]]
+; CHECK-NEXT: [[DOTSINK:%.*]] = select i1 [[CMP3]], ptr [[TMP0]], ptr [[TMP1]]
+; CHECK-NEXT: [[NOT_CMP3:%.*]] = xor i1 [[CMP3]], true
+; CHECK-NEXT: [[DEC:%.*]] = sext i1 [[NOT_CMP3]] to i64
+; CHECK-NEXT: [[J_NEXT]] = sub nsw i64 [[J]], [[DEC]]
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
+; CHECK-NEXT: store ptr [[DOTSINK]], ptr [[TMP4]], align 8
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV]], [[HIGH]]
+; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[EXIT:%.*]], label [[LOOP]]
+; CHECK: exit:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %j = phi i64 [ %j.start, %entry ], [ %j.next, %loop ]
+ %i = phi i64 [ %i.start, %entry ], [ %j.next, %loop ]
+ %gep.i = getelementptr inbounds ptr, ptr %src, i64 %i
+ %l.gep.i = load ptr, ptr %gep.i, align 8
+ %gep.j = getelementptr inbounds ptr, ptr %src, i64 %j
+ %l.gep.j = load ptr, ptr %gep.j, align 8
+ %gep.i.1 = getelementptr inbounds i64, ptr %l.gep.i, i64 %p
+ %2 = load i64, ptr %gep.i.1, align 8
+ %gep.j.1 = getelementptr inbounds i64, ptr %l.gep.j, i64 %p
+ %3 = load i64, ptr %gep.j.1, align 8
+ %cmp3 = icmp slt i64 %2, %3
+ %sel = select i1 %cmp3, ptr %l.gep.i, ptr %l.gep.j
+ %not.cmp3 = xor i1 %cmp3, true
+ %dec = sext i1 %not.cmp3 to i64
+ %j.next = sub nsw i64 %j, %dec
+ %gep.dst = getelementptr inbounds ptr, ptr %dst, i64 %iv
+ store ptr %sel, ptr %gep.dst, align 8
+ %iv.next = add i64 %iv, 1
+ %ec = icmp eq i64 %iv, %j.start
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
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