[llvm] Zext sext undef in sdag (PR #115451)
via llvm-commits
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Fri Nov 8 02:01:53 PST 2024
https://github.com/fengfeng09 created https://github.com/llvm/llvm-project/pull/115451
extend an undef value in sdag should keep the undef info.
>From b5137cd45cd4c4fbcab700bad89955937834dd80 Mon Sep 17 00:00:00 2001
From: "feng.feng" <feng.feng at iluvatar.com>
Date: Fri, 8 Nov 2024 17:35:05 +0800
Subject: [PATCH 1/2] [X86][NFC] Precommit tests for zext/sext undef.
---
llvm/test/CodeGen/X86/zext-sext.ll | 40 +++++++++++++++++++-----------
1 file changed, 26 insertions(+), 14 deletions(-)
diff --git a/llvm/test/CodeGen/X86/zext-sext.ll b/llvm/test/CodeGen/X86/zext-sext.ll
index 25929ecbde76f1..d51a55aab1f8f4 100644
--- a/llvm/test/CodeGen/X86/zext-sext.ll
+++ b/llvm/test/CodeGen/X86/zext-sext.ll
@@ -11,32 +11,34 @@ define void @func(ptr %a, ptr %b, ptr %c, ptr %d) nounwind {
; CHECK-LABEL: func:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movslq (%rsi), %rax
-; CHECK-NEXT: movl $4, %esi
-; CHECK-NEXT: subq %rax, %rsi
+; CHECK-NEXT: movl $4, %r8d
+; CHECK-NEXT: subq %rax, %r8
; CHECK-NEXT: movq (%rdx), %rax
; CHECK-NEXT: movswl 8(%rdi), %edx
-; CHECK-NEXT: movswl (%rax,%rsi,2), %eax
+; CHECK-NEXT: movswl (%rax,%r8,2), %eax
; CHECK-NEXT: imull %edx, %eax
; CHECK-NEXT: addl $2138875574, %eax # imm = 0x7F7CA6B6
; CHECK-NEXT: cmpl $2138875574, %eax # imm = 0x7F7CA6B6
; CHECK-NEXT: setl %dl
; CHECK-NEXT: cmpl $-8608074, %eax # imm = 0xFF7CA6B6
-; CHECK-NEXT: setge %sil
-; CHECK-NEXT: andb %dl, %sil
-; CHECK-NEXT: movzbl %sil, %edx
-; CHECK-NEXT: movslq %eax, %rsi
-; CHECK-NEXT: movq %rsi, %rdi
+; CHECK-NEXT: setge %r8b
+; CHECK-NEXT: andb %dl, %r8b
+; CHECK-NEXT: movzbl %r8b, %edx
+; CHECK-NEXT: movslq %eax, %r8
+; CHECK-NEXT: movq %r8, %r9
; CHECK-NEXT: negl %edx
-; CHECK-NEXT: subq %rax, %rdi
+; CHECK-NEXT: subq %rax, %r9
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testl $-2, %edx
-; CHECK-NEXT: cmovneq %rax, %rdi
-; CHECK-NEXT: testl %esi, %esi
-; CHECK-NEXT: cmovnsq %rax, %rdi
+; CHECK-NEXT: cmovneq %rax, %r9
+; CHECK-NEXT: testl %r8d, %r8d
+; CHECK-NEXT: cmovnsq %rax, %r9
; CHECK-NEXT: movq (%rcx), %rax
-; CHECK-NEXT: subq %rdi, %rsi
-; CHECK-NEXT: leaq -2138875574(%rax,%rsi), %rax
+; CHECK-NEXT: subq %r9, %r8
+; CHECK-NEXT: leaq -2138875574(%rax,%r8), %rax
; CHECK-NEXT: movq %rax, (%rcx)
+; CHECK-NEXT: movl $0, (%rdi)
+; CHECK-NEXT: movl $0, (%rsi)
; CHECK-NEXT: retq
entry:
%tmp103 = getelementptr inbounds [40 x i16], ptr %a, i64 0, i64 4
@@ -77,5 +79,15 @@ entry:
%alphaXbetaY = add i64 %alphaX, %tmp115
%transformed = add i64 %alphaXbetaY, 9040145182981852475
store i64 %transformed, ptr %d, align 8
+ %tmp200 = zext i16 undef to i32
+ %tmp201 = zext i16 undef to i32
+ %tmp202 = shl i32 %tmp201, 16
+ %tmp203 = or i32 %tmp200, %tmp202
+ store i32 %tmp203, ptr %a, align 4
+ %tmp210 = sext i16 undef to i32
+ %tmp211 = sext i16 undef to i32
+ %tmp212 = shl i32 %tmp211, 16
+ %tmp213 = or i32 %tmp210, %tmp212
+ store i32 %tmp213, ptr %b, align 4
ret void
}
>From 49aba6ecbcba47d4e0eeaae17fe4ee5fc4ae0391 Mon Sep 17 00:00:00 2001
From: "feng.feng" <feng.feng at iluvatar.com>
Date: Fri, 8 Nov 2024 17:53:54 +0800
Subject: [PATCH 2/2] [SDAG] zext/sext undef should produce an undef value as
also.
---
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 10 ++++---
llvm/test/CodeGen/X86/zext-sext.ll | 30 +++++++++----------
2 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 203e14f6cde3e3..fe7d4b9d7ccbf9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6224,8 +6224,9 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
return getNode(OpOpcode, DL, VT, N1.getOperand(0), Flags);
}
if (OpOpcode == ISD::UNDEF)
- // sext(undef) = 0, because the top bits will all be the same.
- return getConstant(0, DL, VT);
+ // sext(undef) = undef in a conservative way, because not all of the bits
+ // are zero and there is no mechanism tracking the undef part.
+ return getUNDEF(VT);
break;
case ISD::ZERO_EXTEND:
assert(VT.isInteger() && N1.getValueType().isInteger() &&
@@ -6244,8 +6245,9 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
return getNode(ISD::ZERO_EXTEND, DL, VT, N1.getOperand(0), Flags);
}
if (OpOpcode == ISD::UNDEF)
- // zext(undef) = 0, because the top bits will be zero.
- return getConstant(0, DL, VT);
+ // zext(undef) = undef in a conservative way, because not all of the bits
+ // are zero and there is no mechanism tracking the undef part.
+ return getUNDEF(VT);
// Skip unnecessary zext_inreg pattern:
// (zext (trunc x)) -> x iff the upper bits are known zero.
diff --git a/llvm/test/CodeGen/X86/zext-sext.ll b/llvm/test/CodeGen/X86/zext-sext.ll
index d51a55aab1f8f4..766512afc2a7ec 100644
--- a/llvm/test/CodeGen/X86/zext-sext.ll
+++ b/llvm/test/CodeGen/X86/zext-sext.ll
@@ -11,34 +11,32 @@ define void @func(ptr %a, ptr %b, ptr %c, ptr %d) nounwind {
; CHECK-LABEL: func:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movslq (%rsi), %rax
-; CHECK-NEXT: movl $4, %r8d
-; CHECK-NEXT: subq %rax, %r8
+; CHECK-NEXT: movl $4, %esi
+; CHECK-NEXT: subq %rax, %rsi
; CHECK-NEXT: movq (%rdx), %rax
; CHECK-NEXT: movswl 8(%rdi), %edx
-; CHECK-NEXT: movswl (%rax,%r8,2), %eax
+; CHECK-NEXT: movswl (%rax,%rsi,2), %eax
; CHECK-NEXT: imull %edx, %eax
; CHECK-NEXT: addl $2138875574, %eax # imm = 0x7F7CA6B6
; CHECK-NEXT: cmpl $2138875574, %eax # imm = 0x7F7CA6B6
; CHECK-NEXT: setl %dl
; CHECK-NEXT: cmpl $-8608074, %eax # imm = 0xFF7CA6B6
-; CHECK-NEXT: setge %r8b
-; CHECK-NEXT: andb %dl, %r8b
-; CHECK-NEXT: movzbl %r8b, %edx
-; CHECK-NEXT: movslq %eax, %r8
-; CHECK-NEXT: movq %r8, %r9
+; CHECK-NEXT: setge %sil
+; CHECK-NEXT: andb %dl, %sil
+; CHECK-NEXT: movzbl %sil, %edx
+; CHECK-NEXT: movslq %eax, %rsi
+; CHECK-NEXT: movq %rsi, %rdi
; CHECK-NEXT: negl %edx
-; CHECK-NEXT: subq %rax, %r9
+; CHECK-NEXT: subq %rax, %rdi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testl $-2, %edx
-; CHECK-NEXT: cmovneq %rax, %r9
-; CHECK-NEXT: testl %r8d, %r8d
-; CHECK-NEXT: cmovnsq %rax, %r9
+; CHECK-NEXT: cmovneq %rax, %rdi
+; CHECK-NEXT: testl %esi, %esi
+; CHECK-NEXT: cmovnsq %rax, %rdi
; CHECK-NEXT: movq (%rcx), %rax
-; CHECK-NEXT: subq %r9, %r8
-; CHECK-NEXT: leaq -2138875574(%rax,%r8), %rax
+; CHECK-NEXT: subq %rdi, %rsi
+; CHECK-NEXT: leaq -2138875574(%rax,%rsi), %rax
; CHECK-NEXT: movq %rax, (%rcx)
-; CHECK-NEXT: movl $0, (%rdi)
-; CHECK-NEXT: movl $0, (%rsi)
; CHECK-NEXT: retq
entry:
%tmp103 = getelementptr inbounds [40 x i16], ptr %a, i64 0, i64 4
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