[llvm] [RISCV][GISel] Add G_ZEXT to RISCVInstructionSelector::selectZExtBits. (PR #115391)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/115391

None

>From 76d72ff42832c474d864c0d5bc90de0833174e8a Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 7 Nov 2024 15:11:59 -0800
Subject: [PATCH] [RISCV][GISel] Add G_ZEXT to
 RISCVInstructionSelector::selectZExtBits.

---
 llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp | 4 ++++
 llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll     | 4 +---
 llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll      | 4 +---
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index d11647b78d7417..27f15e07e47b8a 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -288,6 +288,10 @@ RISCVInstructionSelector::selectZExtBits(MachineOperand &Root,
     return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(RegX); }}};
   }
 
+  if (mi_match(RootReg, *MRI, m_GZExt(m_Reg(RegX))) &&
+      MRI->getType(RegX).getScalarSizeInBits() == Bits)
+    return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(RegX); }}};
+
   unsigned Size = MRI->getType(RootReg).getScalarSizeInBits();
   if (KB->maskedValueIsZero(RootReg, APInt::getBitsSetFrom(Size, Bits)))
     return {{[=](MachineInstrBuilder &MIB) { MIB.add(Root); }}};
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll b/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
index 0e5cbe63004b62..a4f92640697bc7 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
@@ -300,9 +300,7 @@ define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, ptr %1) nounwind {
 ; RV64IFD-LABEL: fcvt_d_wu_demanded_bits:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    addiw a0, a0, 1
-; RV64IFD-NEXT:    slli a2, a0, 32
-; RV64IFD-NEXT:    srli a2, a2, 32
-; RV64IFD-NEXT:    fcvt.d.wu fa5, a2
+; RV64IFD-NEXT:    fcvt.d.wu fa5, a0
 ; RV64IFD-NEXT:    fsd fa5, 0(a1)
 ; RV64IFD-NEXT:    ret
   %3 = add i32 %0, 1
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll b/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
index c5a36d063c0ad6..7e96d529af36ff 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
@@ -272,9 +272,7 @@ define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, ptr %1) nounwind {
 ; RV64IF-LABEL: fcvt_s_wu_demanded_bits:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addiw a0, a0, 1
-; RV64IF-NEXT:    slli a2, a0, 32
-; RV64IF-NEXT:    srli a2, a2, 32
-; RV64IF-NEXT:    fcvt.s.wu fa5, a2
+; RV64IF-NEXT:    fcvt.s.wu fa5, a0
 ; RV64IF-NEXT:    fsw fa5, 0(a1)
 ; RV64IF-NEXT:    ret
   %3 = add i32 %0, 1